A method of processing in-memory commands in a high-bandwidth memory (HBM) system includes sending a function-in-HBM instruction to the HBM by a HBM memory controller of a GPU. A logic component of the HBM receives the FIM instruction and coordinates the instructions execution using the controller, an ALU, and a SRAM located on the logic component.

A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

A graph-based data flow control system includes a control plane system coupled to SCP subsystems. The control plane system identifies a workload, and identifies service(s) on the SCP subsystems for manipulating/exchanging data to perform the workload. The control plane system generates a respective SCP-local data flow control graph for each SCP subsystem that defines how their service(s) will manipulate/exchange data within that SCP subsystem, and generates inter-SCP data flow control graph(s) that define how service(s) provided by at least one SCP subsystem will manipulate/exchange data with service(s) provided by at least one other SCP subsystem. The control plane system then transmits each respective SCP-local data flow control graph to each of the SCP subsystems, and the inter-SCP data flow control graph(s) to at least one SCP subsystem, for use by the SCP subsystems in causing their service(s) to manipulate/exchange data to perform the workload.

A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

An artificial intelligence chip and a data operation method are provided. The artificial intelligence chip receives a command carrying first data and address information and includes a chip memory, a computing processor, a base address register, and an extended address processor. The base address register is configured to access an extended address space in the chip memory. The extended address processor receives the command. The extended address processor determines an operation mode of the first data according to the address information. When the address information points to a first section of the extended address space, the extended address processor performs a first operation on the first data. When the address information points to a section other than the first section of the extended address space, the extended address processor notifies the computing processor of the operation mode and the computing processor performs a second operation on the first data.

Memory module, computing device, and methods of reading and writing data to the memory module are disclosed. A memory module, comprises one or more dynamic random-access memories (DRAMs); and a processor configured to select a Central Processing Unit (CPU) or the Processor to communicate with the one or more DRAMs via a memory interface.

A semiconductor device capable of shortening a time required for data transfer and data organizing is provided. The solid state device includes a processor, a memory, an external interface, registers for storing data received by the external interface, a mirror register buffer, a processor, a memory, an external interface, registers, and an internal bus connected to the mirror register buffer. Registers output data to the mirror register buffer without going through the internal bus. Mirror register buffer gives the data input from the registers an address in a mirror register buffer different from the address allocated to the register, and transfers the data to the memory without passing through the internal bus.

The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

The present disclosure provides a method and a system for automatically configuring an I/O port. The method applied to a central processor includes: receiving request information from a controlled device, the request information carrying a type of a signal required by the controlled device, and sending, according to the type of the signal, a configuration instruction to a control device, and instructing the control device to configure the I/O port according to the configuration instruction. The controlled device is connected to the central processing unit, or the controlled device is connected to the central processor by means of the control device.

A computing device including: more than two Universal Serial Bus (USB) ports configured to be connected respectively to more than two mobile devices simultaneously; at least one processor coupled to the USB ports; and a memory storing instructions configured to instruct the at least one processor to reprogram, through the more than two USB ports, the more than two mobile devices simultaneously.