The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.

A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

An adapter device communicates with a sink device and a source device using first and second communication schemes, respectively. The adapter device includes: a transceiver receiving a state read request by detecting that a serial data line connected between the adapter device and the sink device is driven to a low level when a serial clock line connected therebetween is at a high level, and drive the serial data line to the low level and drive the serial clock line to a low level; a transmitter transmitting the state read request to the source device after the serial clock line is driven to the low level; and a receiver receiving a state read signal to read data of a state register in the sink device from the source device, wherein the transceiver transmits the state read signal to the sink device via the serial data line.

A relay device includes a first connecting unit, a second connecting unit, a first notifying unit, a second notifying unit, and a communicating unit. The first connecting unit is connected with a first interface of a first device, the first interface being not compliant with USB (Universal Serial Bus) standard. The second connecting unit is connected with a second interface of a second device, the second interface being compliant with the USB standard. The first notifying unit notifies the second device that the relay device is a USB device. The second notifying unit notifies the first device that the second device has been connected to the second connecting unit. The communicating unit relays communication carried out between the second device and the first device.

Disclosed herein are methods, devices, and systems for providing timing and bandwidth management of ultra-wideband, wireless data channels (including radio frequency and wireless optical data channels). According to one embodiment, a hub apparatus is disclosed for providing out-of-band bandwidth management for a free-space-optical (FSO) data channel associated with a first device. The hub apparatus includes a processor, a memory coupled with the processor, an FSO transmitter coupled with the processor, and an FSO receiver coupled with the processor. The FSO transmitter may be configured to transmit a control signal comprising timing information and bandwidth management information.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

A data-processing device includes a computing unit and an interface unit using a packet-based communication protocol, in particular PCI Express. The data-processing device also includes an intrusion detection unit that is connected via a signal connection to a filter device of the interface unit, and/or to a secure element, in the form of a Trusted Execution Environment, of an authentication arrangement related to the communication protocol. The intrusion detection unit evaluates input signals received via the signal connection for a rule infringement in a set of intrusion detection rules The filter device, at least part of which is hardware, is designed to forward only the communication data meeting an approval condition from the interface unit to an additional component of the data-processing device according to configuration information predetermined in the data-processing device and containing the approval condition. At least one intrusion detection rule relates to the infringement of the approval condition and/or to an authentication error.

A carriage system on an aircraft determines the type of each store attached to the carriage system. The carriage system detects stores attached to the carriage system and determines whether a first interlock signal formatted according to a first interface format is present for each store. If the first interlock signal is present, then the dual mode carriage system determines that a store interface for the store is the first interface format. If the first interlock signal is not present for the store, the carriage system determines whether a second interlock signal formatted according to a second interface format is present on a predetermined set of connection pins of the first interface format. If the second interlock signal is present, then the carriage system determines that the store interface for the store is the second interface format. The carriage system reports the store interface of each store to the aircraft.

Disclosed is a system for collecting data from an automated plant having a field device connected for communication and for exchanging telegrams with a superordinate unit by means of a communication loop using a first protocol. The system includes a hat rail; and a terminal module mounted on the hat rail and embodied to monitor telegrams transmitted from the field device to the superordinate unit via the communication loop. The terminal module is further embodied to convert monitored telegrams into a second protocol and to output the converted telegrams. The system further includes a head module mounted on the hat rail and connected with the terminal module. The electronics unit of the head module is embodied to convert telegrams output from the terminal module into a third protocol to output them via the first network interface.

An interface conversion device connects the devices having the different interfaces, and it is possible to appropriately transmit and receive data from one device to the other device.

The interface conversion device 30 comprises a first transmission/reception part 12 connected to a first interface 2, a second transmission/reception part 13 connected to a second interface 4, a data storage part 33 that stores data transmitted from and the second transmission/reception part 13, an information conversion part 11 that adapts the data conforming to the second interface 4 to the first interface 2, a first information acquisition part 31 that acquires the information related to the data transmission speed of the first interface 2, a second information acquisition part 32 that acquires the information related to the data transmission speed of the second interface 4, a transmission speed management part 35 that determines the optimum data transmission speed related to the second interface 4 based on the information acquired by the first information acquisition part 31 and the second information acquisition part 32.