An electronic device includes a bus driver and circuitry. The bus driver is coupled to a parallel bus including N data lines. The circuitry is configured to receive a data unit for transmission over the N data lines, to determine a first count indicative of a number of data bits in the data unit having a predefined value, and a second count indicative of a number of inverted data bits relative to corresponding bits in a previously transmitted data unit, to make a decision of whether to invert the data unit based on the first and second counts, depending on whether such inversion is expected to reduce power consumption of transmitting the data unit over the bus, to produce an output data unit by retaining or inverting the data unit based on the decision, and to transmit the output data unit over the data lines via the bus driver.

Examples are described herein for dynamically allocating shared bus lanes provided by a peripheral component bridge. A multiplexor may be operably coupled with the bridge via the shared bus lanes. A plurality of peripheral component slots may each be operably coupled with the multiplexor via a respective plurality of peripheral bus lanes. The multiplexor may multiplex the shared bus lanes to multiple different peripheral component slots. Circuitry may: interrogate each of the peripheral component slots to obtain information about a modular component installed in the peripheral component slot, wherein the information about the modular component includes a usable range of bus lanes and a transmission speed capability; and cause the multiplexor to dynamically allocate the number of shared bus lanes to the respective pluralities of peripheral bus lanes of the peripheral component slots based on the usable ranges and transmission speed capabilities of the installed modular components.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

An apparatus supports single root input/output virtualization (SR-IOV) capable devices. The apparatus includes input/output ports, and SR-IOV capable PCIe devices. Each SR-IOV capable PCIe device has one or more namespaces or controller memory buffers. The SR-IOV capable PCIe device provides one or more physical functions and virtual functions that can access the one or more namespaces or controller memory buffers. A PCIe switch controller communicates with host servers coupled to the input/output ports, and assigns one or more virtual functions to each host device, and enables the host devices to access one or more namespaces or controller memory buffers through the assigned virtual functions. The PCIe device is configured to attach one or more namespaces or one or more partitions of one or more controller memory buffers to each virtual function, set at least one namespace or controller memory buffer to a shared state and allow different host devices to access the same namespace or controller memory buffer using respective assigned virtual functions.

An adaptation method between PCIE and SPI realized based on FPGA, comprising following steps: S01: a PCIE equipment sends PCIE information to a mapping module through a PCIE module; S02: the mapping module extracts SPI information from the PCIE information and transmits the SPI information to a SPI equipment through an SPI module; all of the PCIE module, the mapping module and the SPI module are located on a FPGA chip; S03: the SPI equipment performs a read/write operation according to the SPI information, and feeds back SPI operation information subjected to the read/write operation to the mapping module; S04: the mapping module modifies PCIE information according to the SPI operation information to obtain PCIE feedback information; S05: the PCIE equipment reads the PCIE feedback information through the PCIE module. The present invention provides a conversion adapter and a method between PCIE and SPI realized based on FPGA to realize conversion for a PCI interface and a SPI interface, so as to perform a read/write operation of an AD chip with the SPI interface or a DA chip with the SPI interface, which has universal applicability.

Various data bus monitoring, analysis, and logging systems, devices, and methods are described herein. In one example, an apparatus includes a first circuit configured to monitor first packets among traffic carried by one or more first directional lanes of a communication link established between a host and one or more endpoint devices and determine header information for the first packets. The apparatus includes a second circuit configured to detect second packets among traffic carried by one or more second directional lanes of the communication link based at least in part on the header information determined for the first packets. The apparatus includes an analysis element configured to establish transaction metadata comprising properties of transactions on the communication link based at least on correlations among the first packets and the second packets.

A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

A signal tuning method for a peripheral component interconnect express (PCIe) includes assigning a first signal setting to the PCIe to generate a first PCIe signal, and tuning a link by the first PCIe signal, and determining whether to assign a second signal setting to the PCIe according to a signal status of the link, for generating a second PCIe signal to tune the link; wherein the PCIe is connected to a plurality of electronic devices via the link.

A method for use in a storage system is disclosed, comprising: receiving, at a first server in the storage system, a given block layer request for reservation of a storage resource, by the first server, an identifier corresponding to the given block layer request; performing a search of a database to detect whether the given block layer request has been completed, the search being performed by the first server, the search being performed based on the identifier corresponding to the given block layer request; when the database indicates that the given block layer request has not been completed: completing the given block layer request and transmitting a notification that the given block layer request is completed; and when the database indicates that given block layer request has been completed, re-transmitting a notification that the given block layer request is completed.