A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

In some embodiments, systems, devices, and methods are provided that allow a host device to communicate video information, network information, and USB information over USB via a USB host controller. The video information and the network information are encapsulated within USB and communicated by the USB host controller.

In some embodiments, the USB information communicated by the USB host controller is further communicated over a non-USB extension medium by an upstream facing port device and one or more downstream facing port devices.

Techniques for supporting USB and video communication over an extension medium are provided. In some embodiments, an upstream facing port device (UFP device) is coupled to legacy connectors of a host device, and a downstream facing port device (DFP device) is coupled to a USB Type-C receptacle of the sink device that may provide both USB and DisplayPort information. The UFP device and DFP device communicate to properly configure the USB Type-C connection for use in the extension environment. In some embodiments, a source device is coupled to the UFP device via a USB Type-C connection, and legacy video and USB devices are coupled to the DFP device. The UFP device and DFP device again communicate to cause the source device to properly configure the USB Type-C connection for use in the extension environment.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for determining, for each pair of adjacent chips in a plurality of chips connected in a series-ring arrangement of a semiconductor device, a corresponding loop latency for round trip data transmissions between the pair of chips. Identifying, from among the loop latencies, a maximum loop latency. Determining a ring latency for a data transmission originating from a chip of the plurality chips to be transmitted around the series-ring arrangement and back to the chip. Comparing half of the maximum loop latency to one N-th of the ring latency, where N is the number of chips in the plurality of chips, and storing the greater value as an inter-chip latency of the semiconductor device, the inter-chip latency representing an operational characteristic of the semiconductor device.

A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.

A method of provisioning a system includes defining one or more virtual peripherals such that each of the virtual peripherals corresponds to a respective device; identifying one or more enabled virtual peripherals; and identifying one or more control modules. Each of the control modules includes one or more terminals for connecting to one or more devices. The method further includes linking each of the enabled virtual peripherals to a respective terminal of the one or more control modules to form a link; generating a provisioning configuration that represents the link between the respective terminal and the corresponding one of the enabled virtual peripherals; and writing the provisioning configuration to each of the control modules. The method further includes connecting the respective device to the respective terminal consistent with the link between the respective terminal and the corresponding one of the enabled virtual peripherals.

A communication system for an industrial process includes multiple slave modules connected in series with a master controller. The master controller stores a communication schedule that defines an ordered sequence of messages and identifiers associated with each message. The master controller transmits messages downstream through the slave modules to a terminal one of the slave modules. The terminal slave module generates a return message that is transmitted upstream to the master controller. Each slave module receives each downstream message, identifies based on the message identifier whether the message is associated with response information from the slave module, and inserts the response information into corresponding upstream messages.

A computing storage architecture is disclosed. Memory devices may incorporate distributed processors and memory. The devices can be arranged using multiple packages, each package including one, or multiple, dies. In one aspect of the disclosure, any of the processors on a first die may transfer data to and from any processor on a second die internally within the device without having to pass through an external storage controller. In another aspect of the disclosure, a multi-package processing architecture allows for both in-package and inter-channel data transfers between processors within the same device. In still another aspect of the disclosure, one or more processors may include a preemptive scheduler circuit, which enables a processor to interrupt an ongoing lower priority transmission and to immediately transfer data.

A system having a host unit and a plurality of stacked modules which are electrically connected to the host unit. The host unit communicates with the plurality of stacked modules through a RS-485 interface. Upon power up, each module of the plurality of stacked modules is powered and enumerated in sequence, allowing the host unit to know the sequence the plurality of stable modules are connected.

A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.