An integrated circuit with an adaptive UART serial interface includes at least one input section through which a signal is input from a user, at least one output section through which information is output in a predetermined form, and a microcontroller unit (MCU), independently of the microcontroller unit (MCU), and communicates with the microcontroller unit to control, on the basis of the input signal generated from the at least one input section, output driving of the output section corresponding thereto, the integrated circuit including: a serial interface that includes an Rx pin for receiving a data signal from the microcontroller unit by forming a signal reception line with respect to the microcontroller unit and a Tx pin for transmitting a data signal to the microcontroller unit by forming a signal transmission line with respect to the microcontroller unit.

A first node obtains a transaction layer packet (TLP); and the first node sends the TLP to a second node. The TLP includes data, a type field, and an extension header, and the type field and the extension header are used to indicate a data type of the data and one or more first attribute parameters corresponding to the data type.

A method for data transmission includes dividing first data into data packets, selecting transition acceleration data among transition acceleration data preliminary packets, generating transition guarantee data packets by performing an operation on a data packet group including predetermined data packets among the data packets and the transition acceleration data, and transmitting the transition acceleration data and the transition guarantee data packets. In the selecting the transition acceleration data among the transition acceleration data preliminary packets, the transition acceleration data different from previous transition acceleration data immediately preceding the transition acceleration data in the transition acceleration data preliminary packets is selected.

A chip module has a plurality of first ports, at least some or all of the first ports are first selection ports, and each first selection port may act as a write port or a read port. The chip module further includes a first control module. The first control module controls, based on a transmit/receive requirement of the chip module, the first selection port to be switched to a read port or a write port, to match the transmit/receive requirement of the chip module. The first selection port may selectively act as a read port or a write port, so that switching can be performed based on an operating state of the chip module, increasing a read/write bandwidth. The first control module controls an operating state of the first selection port, to flexibly adjust a quantity of read ports and a quantity of write ports of the chip module.

Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.

A transition enforcing coding (TEC) receiver includes a first delay line circuit, a transition detection circuit, and a data sampling circuit. The first delay line circuit delays a plurality of vector signals to generate a plurality of delayed vector signals, respectively. The transition detection circuit detects a transition of at least one specific delayed vector signal among the delayed vector signals. The data sampling circuit samples the vector signals according to a sampling timing determined based on an output of the transition detection circuit.

A communication method according to the present embodiment is a communication method between a first side and a second side operating with a clock provided by the first side, and includes a phase calibration step, a step of transmitting a command packet to the second side by the first side, and a data transmission and reception step of transceiving data packets according to the command packet between the first side and the second side. The phase calibration step is performed to calibrate phases of a transmit sampling clock of the first side and a receive sampling clock of the first side.

A link startup method of a storage device connected to a host through a plurality of lanes includes performing an initialization operation in the storage device; establishing data communication through a connected transmission lane and a connected reception lane among the plurality of lanes; transmitting a high speed link up message to the host through the connected transmission lane of the storage device; and performing a link startup operation in a high speed mode through the connected transmission lane of the storage device and the connected reception lane of the host, based on the high speed link up message transmitted by the storage device.

A transceiver includes a transmitter and a receiver which are connected to each other through a first line and a second line. The transmitter transmits a first clock training pattern to the receiver in a first period, transmits a second clock training pattern and a first first payload to the receiver in a second period, and transmits a third clock training pattern and a second first payload to the receiver in a third period. The first clock training pattern, the second clock training pattern, and the third clock training pattern are variable based on a plurality of driving modes.

A computer implemented method of updating software of embedded devices connected to a central dispatch device, comprising using one or more processors of a central dispatch device, the processor(s) are adapted for executing a code for obtaining a respective update package for one or more of a plurality of embedded devices which are operatively connected to the central dispatch device via a communication interconnection, transferring a transient update agent to the embedded device(s) and transferring the update package to the embedded device(s), the one or more embedded devices execute the transient update agent to apply the update package in the one or more embedded devices. The one or more embedded devices discard the transient update agent after the update package is applied.