The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

A data bus subscriber and a method for processing data, wherein the data bus subscriber can be connected to a local bus, particularly a ring bus, and the data bus subscriber has an input interface, which can be connected to the local bus, for receiving first local bus data, an output interface, which can be connected to the local bus, for transmitting second local bus data, a processing component for synchronous processing of the first local bus data and/or data stored in a memory and for output of at least one control signal, a logic unit, which is adapted in order to modify a quantity of received first local bus data based on the control signal in order to generate the second local bus data to be transmitted, wherein the logic unit is further adapted for synchronous, delayed transmitting of the second local bus data via the output interface.

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

An adapter device communicates with a sink device and a source device using first and second communication schemes, respectively. The adapter device includes: a transceiver receiving a state read request by detecting that a serial data line connected between the adapter device and the sink device is driven to a low level when a serial clock line connected therebetween is at a high level, and drive the serial data line to the low level and drive the serial clock line to a low level; a transmitter transmitting the state read request to the source device after the serial clock line is driven to the low level; and a receiver receiving a state read signal to read data of a state register in the sink device from the source device, wherein the transceiver transmits the state read signal to the sink device via the serial data line.

A system includes a switch unit that is connected to a host connector of a computer, an embedded controller (EC) that connected to the switch unit, and a management device that includes a device connector and a microcontroller. The device connector is connected to the host connector. The microcontroller is connected to the device connector, and sends external data via the device connector to the EC. When the EC is supplied with electricity, the EC controls the switch unit to establish an electrical connection between the EC and the host connector so as to allow the EC to communicate with the microcontroller through the EC and the host connector to receive the external data from the microcontroller.

A multi-antenna channel device and a configuration method for the multi-antenna channel device are provided. The device includes: a main control chip and radio frequency chips, wherein the main control chip is connected to chip selection signal interfaces of the radio frequency chips via a shared chip selection signal line and is configured to send a chip selection signal to a target radio frequency chip; the main control chip is connected to clock signal interfaces of the radio frequency chips via a shared clock signal line and is configured to send a clock signal to the target radio frequency chip; and the main control chip is connected to data interfaces of the radio frequency chips via a shared data line and is configured to send target serial data to the target radio frequency chip or receive target serial data from the target radio frequency chip.

The present disclosure relates to a mirrored serial interface (MSI) for accessing peripherals through four wire serial interface. More particularly, the present disclosure is related to serial peripheral protocol with looped back mechanism in which contents of source data line are looped back onto the destination line and compared at every clock edge to ensure data sanity and to assert presence of slave and master device during and between cycles.

In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.