A computing device, including a processor configured to perform data transfer scheduling for a hardware accelerator including a plurality of processing areas. Performing data transfer scheduling may include receiving a plurality of data transfer instructions that encode requests to transfer data to respective processing areas. Performing data transfer scheduling may further include identifying a plurality of transfer path conflicts between the data transfer instructions. Performing data transfer scheduling may further include sorting the data transfer instructions into a plurality of transfer instruction subsets. Within each transfer instruction subset, none of the data transfer instructions have transfer path conflicts. For each transfer instruction subset, performing data transfer scheduling may further include conveying the data transfer instructions included in that transfer instruction subset to the hardware accelerator. The data transfer instructions may be conveyed in a plurality of sequential data transfer phases that correspond to the transfer instruction subsets.

Systems, methods, and/or apparatuses may be operative to perform a dialysis process that includes a displacer infusion process. The dialysis machine may include at least one processor and a memory coupled to the at least one processor, the memory comprising instructions that, when executed by the processor, may cause the at least one processor to access dialysis information for a dialysis process performed by a dialysis machine, the dialysis information indicating a target substance to be displaced from a binding compound by a displacer, and determine an infusion profile for infusing the displacer into a patient during a displacer infusion process of the dialysis process, the infusion profile determined based on the dialysis information and an infusion constraint. Other embodiments are described.

Systems, methods, and/or apparatuses may be operative to perform a dialysis process that includes a displacer infusion process. The dialysis machine may include at least one processor and a memory coupled to the at least one processor, the memory comprising instructions that, when executed by the processor, may cause the at least one processor to access dialysis information for a dialysis process performed by a dialysis machine, the dialysis information indicating a target substance to be displaced from a binding compound by a displacer, and determine an infusion profile for infusing the displacer into a patient during a displacer infusion process of the dialysis process, the infusion profile determined based on the dialysis information and an infusion constraint. Other embodiments are described.

An operational circuit of a virtual currency data processing device includes: at least two operational chip groups (31) configured to operate within respective operating voltage threshold ranges of the operational chip groups (31) to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal which includes a calculation result; a control module (32) configured to operate within an operating voltage threshold range of the control module (32) to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to the control module and a respective operational chip group and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups from an operating voltage threshold of the control module to make the operational chip groups and the control module capable of identifying communication signals sent by each other.

An information processing device includes a field programmable gate array configured to store route information in flow control, and forward packets according to the route information; one or more memories configured to store a flow cache that includes at least a part of the route information; and one or more processors coupled to the one or more memories and the one or more processors configured to divide the route information into a plurality of division areas; and acquire hit information extracted from each of the entries in a first division area of the plurality of division areas to delete a part of entries of the flow cache stored in the one or more memories, the first division area including flows whose number is greater than a threshold value.

An information processing device includes a field programmable gate array configured to store route information in flow control, and forward packets according to the route information; one or more memories configured to store a flow cache that includes at least a part of the route information; and one or more processors coupled to the one or more memories and the one or more processors configured to divide the route information into a plurality of division areas; and acquire hit information extracted from each of the entries in a first division area of the plurality of division areas to delete a part of entries of the flow cache stored in the one or more memories, the first division area including flows whose number is greater than a threshold value.

A system-on-a-chip sharing a graphics processing unit supporting multi-master is provided. A system on chip (SoC) comprises a plurality of central processing units (CPUs) for executing at least one operating system, a graphics processing unit (GPU) that is connected to each of the plurality of CPUs via a bus interface and communicates with each of the plurality of CPUs, and at least one state monitoring device that is selectively connected to at least one CPU among the plurality of CPUs and transmits execution state information of at least one operating system executed in the connected CPU to the GPU. The GPU is shared by at least one operating system and controls a sharing operation by the at least one operating system based on the execution state information of the at least one operating system.

Devices and methods for providing alert notifications. The device includes an input module, a display, and memory having instructions. The device receives, via the input module, a first signal representing a command to set an alert condition associated with an identifier and, in response, generates the alert condition. The device transmits a second signal representing the alert condition to a monitoring system for setting up a targeted notification. The device receives a third signal representing an asserted alert indicating that the alert condition is satisfied and displays on the display, based on the third signal representing the asserted alert, an alert notification including the identifier and a first selectable option associated with a first application interface. In response to receiving, via the input module, a fourth signal representing selection of the first selectable option, the device displays the first application interface and auto-populates a first field based on the identifier.

A system comprises a processor and a plurality of memory units. The processor is coupled to each of the plurality of memory units by a plurality of network connections. The processor includes a plurality of processing elements arranged in a two-dimensional array and a corresponding two-dimensional communication network communicatively connecting each of the plurality of processing elements to other processing elements on same axes of the two-dimensional array. Each processing element that is located along a diagonal of the two-dimensional array is configured as a request broadcasting master for a respective group of processing elements located along a same axis of the two-dimensional array.

A processor communication method is implemented by an electronic device including a first processor and a second processor. The method includes the operations as follows. The first processor transmits a first master interrupt signal to the second processor, in response to detecting a downlink packet. The first processor receives a first slave acknowledge signal returned from the second processor based on the first master interrupt signal. The first processor transmits the downlink packet to the second processor based on the first slave acknowledge signal, and transmits a second master interrupt signal after completion of the transmitting of the downlink packet. The second master interrupt signal is used to instruct the second processor to transmit a second slave acknowledge signal after completion of processing the downlink packet.