A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.

A system on chip and a method for operating a system on chip are provided. The system on chip a plurality of intellectual property (IP) cores including a first IP core configured to process data in real-time, a buffer including a plurality of queues, and processing circuitry configured to, generate first traffic data corresponding to first data output from the first IP core, and reserve at least one queue of the plurality of queues as a first dedicated area based on the first traffic data, the first dedicated area configured to be used as a queue for transmission of the first data.

A method is provided that includes performing, by a processor in response to a vector sort instruction, sorting of values stored in lanes of the vector to generate a sorted vector, wherein the values in a first portion of the lanes are sorted in a first order indicated by the vector sort instruction and the values in a second portion of the lanes are sorted in a second order indicated by the vector sort instruction; and storing the sorted vector in a storage location.

Example implementations relate to an access point (AP) that can via up from power save mode via a including Bluetooth low energy (BLE) system-on-chip (SoC) within the AP. The AP can include a power source, a power reset logic component in communication with the power source, a BLE SoC, a processor, and a non-transitory memory resource instructions executable by the processor that signals the AP is in a power save mode, receives an indication, via the BLE SoC, to wake up the AP, and wake up, via the BLE SoC, the AP in response to receiving the indication.

In different example embodiments, a system-on-chip is provided. The system-on-chip can have a control circuit with a plurality of control circuit areas, wherein the control circuit is configured to control a device, a security circuit which has a separately secured key memory and a hardware accelerator for cryptographic operations, wherein the security circuit is configured to electively enable either a read-only access or a read and write access to at least one of the control circuit areas, wherein the security circuit is furthermore configured to provide a communication path by means of the key memory and the hardware accelerator for the secured communication with a diagnostic system disposed outside the security circuit, to make the selection between the read access and the read and write access to the at least one selected area of the control circuit depending on a certificate supplied to the security circuit and authenticated by means of information stored in the key memory, and to execute the read access or the read and write access.

A system timer bus used by the processor elements in an ARM-based system on a chip (SoC) is driven using a Precision Time Measurement (PTM) value. This allows the processor elements to be synchronized to the PCIe ports that use PTM. When two SoCs are connected using PCIe links, this example allows the processor elements in both SoCs to be synchronized. As the processor elements are synchronized, associated tasks on the two SoCs are synchronized, so that overall operations are synchronized.

A system-on-chip (SoC) for operating a plurality of different central processing units and a method for operating the same are provided. The SoC includes a plurality of central processing units (CPUs) that execute respective software programs independently of each other, a bus interconnector for connecting the plurality of CPUs, and at least one access control device that is connected to the bus interconnector and controls each access to a physical resource shared by the plurality of CPUs via the bus interconnector, for each CPU.

Embodiments herein describe end-to-end bindings to create zones that extend between different components in a SoC, such as an I/O gateway, a processor subsystem, a NoC, storage and data accelerators, programmable logic, etc. Each zone can be assigned to a different domain that is controlled by a tenant such as an external host, or software executing on that host. Embodiments herein create end-to-end bindings between acceleration engines, I/O gateways, and embedded cores in SoCs. Instead of these components being treated as disparate monolithic components, the bindings divide up the hardware and memory resources across components that make up the SoC, into different zones. Those zones in turn can have unique bindings to multiple tenants. The bindings can be configured in bridges between components to divide resources into the zones to enable tenants of those zones to have dedicated available resources that are secure from the other tenants.

System on a chip, comprising several master pieces of equipment, several slave resources, an interconnection circuit capable of routing transactions between master pieces of equipment and slave resources, and a processing unit at least configured to allow a user of the system on a chip to implement within the system on a chip at least one configuration diagram of this system defined by a set of configuration pieces of information including at least one piece of identification information assigned to each master piece of equipment, The identification pieces of information are intended to be attached to all the transactions emitted by the corresponding master pieces of equipment, the set of configuration pieces of information not being used for addressing the slave resources receiving the transactions and being used to define an assignment of at least one piece of master equipment to at least some of the slave resources.

An integrated circuit includes an interposer, a first die coupled to the interposer, a second die coupled to the interposer, and a third die coupled to the interposer and having a plurality of die interfaces. The first die includes a first data processing engine (DPE) array having a first plurality of DPEs and a first DPE interface coupled to the first plurality of DPEs therein. The second die includes a second DPE array having a second plurality of DPEs and a second DPE interface coupled to the second plurality of DPEs therein. The first DPE interface of the first die is configured to communicate with a first die interface of the plurality of die interfaces via the interposer. The second DPE interface of the second die is configured to communicate with a second die interface of the plurality of die interfaces via the interposer.