In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

An integrated circuit (IC) can include a processor system configured to execute program code, a programmable logic, and a platform management controller coupled to the processor system and the programmable logic. The platform management controller is adapted to configure and control the processor system and the programmable logic independently.

A method for sorting of a vector in a processor is provided that includes performing, by the processor in response to a vector sort instruction, generating a control input vector for vector permutation logic comprised in the processor based on values in lanes of the vector and a sort order for the vector indicated by the vector sort instruction and storing the control input vector in a storage location.

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

Methods and systems related to the efficient execution of complex computations by a multicore processor and the movement of data among the various processing cores in the multicore processor are disclosed. A multicore processor includes a set of processing cores and associated sets of processing pipelines, core controllers, routers, and network interface units. The multicore processor also includes a computation layer, for conducting computations using the set of processing cores, with executable instructions for the set of processing pipelines which are executed by the set of core controllers. The multicore processor also includes a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for the set of routers and the set of network interface units. The multicore processor also includes a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer.

A device may include a plurality of data processing engines. Each of the data processing engines may include a memory pool having a plurality of memory banks, a plurality of cores each coupled to the memory pool and configured to access the plurality of memory banks, a memory mapped switch coupled to the memory pool and a memory mapped switch of at least one neighboring data processing engine, and a stream switch coupled to each of the plurality of cores and to a stream switch of the at least one neighboring data processing engine.

A system-on-chip (SoC) can include a processor, a network controller configured to provide a network interface, and a memory controller configured to perform memory scrubbing. A memory patrol driver executing on the processor can initiate direct memory access (DMA) transfers to read successive portions of the memory by configuring corresponding DMA descriptors at a certain time interval. The network controller can perform each DMA transfer to read a corresponding portion of the memory, which can cause the memory controller to scrub the corresponding portion of the memory. The scrubbed data is sent to the network controller, which is discarded by the network controller.

The present disclosure relates to a system and method for optimizing switching of a DRAM bus using LLC. An embodiment of the disclosure includes sending a first type request from a first type queue to the second memory via the memory bus if a direction setting of the memory bus is in a first direction corresponding to the first type request, decrementing a current direction credit count by a first type transaction decrement value, if the decremented current direction credit count is greater than zero, sending another first type request to the second memory via the memory bus and decrementing the current direction credit count again by the first type transaction decrement value, and if the decremented current direction credit count is zero, switching the direction setting of the memory bus to a second direction and resetting the current direction credit count to a second type initial value.

An energy-aware system is provided. The system includes an energy harvester adapted to supply harvested energy as an output for storage at an energy storage; and a scheduler, the scheduler being made up of, at least in part, hardware of the energy-aware system, the scheduler operable to schedule execution of operations performed by the energy-aware system, wherein the scheduler is configured to: determine if a current voltage level at the energy storage is higher than a start voltage level; and cause initiation of execution of at least a portion one of the operations when the start voltage of the one of the operations levels is lower than or equal to the current voltage level.

A system-on-a-chip sharing a graphics processing unit supporting multi-master is provided. A system on chip (SoC) comprises a plurality of central processing units (CPUs) for executing at least one operating system, a graphics processing unit (GPU) that is connected to each of the plurality of CPUs via a bus interface and communicates with each of the plurality of CPUs, and at least one state monitoring device that is selectively connected to at least one CPU among the plurality of CPUs and transmits execution state information of at least one operating system executed in the connected CPU to the GPU. The GPU is shared by at least one operating system and controls a sharing operation by the at least one operating system based on the execution state information of the at least one operating system.