A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

A data processing system comprising: a processor comprising a plurality of cores, each core comprising a first processing pipeline and a second processing pipeline, the second processing pipeline having a different architecture to the first processing pipeline; a framework configured to manage the processing resources of the data processing system including the processor; and an interface configured to present to the framework each of the processing pipelines as a core.

A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.

A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising at least one register to hold a varying number of elements. The computer processor may further comprise processing logic configured to operate on the varying number of elements in the vector register file using one or more instructions that separate a vector or combine two vectors. The computer processor may be implemented as a monolithic integrated circuit.

A memory management method includes receiving, by a first operating system, a memory scheduling request sent by at least one second operating system through an inter-core communication channel, determining, by the first operating system, a target memory priority of each second processor corresponding to the second operating system based on the memory scheduling request, and assigning, by the first operating system, a memory bandwidth to the second operating system based on the target memory priority of the second processor. The memory scheduling request is used to request a memory bandwidth required by the second operating system. Each operating system is configured to run on a hardware set of a system-on-chip (SoC).

A memory management method includes receiving, by a first operating system, a memory scheduling request sent by at least one second operating system through an inter-core communication channel, determining, by the first operating system, a target memory priority of each second processor corresponding to the second operating system based on the memory scheduling request, and assigning, by the first operating system, a memory bandwidth to the second operating system based on the target memory priority of the second processor. The memory scheduling request is used to request a memory bandwidth required by the second operating system. Each operating system is configured to run on a hardware set of a system-on-chip (SoC).