An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

A method of providing a distributed scheme for executing a RAM program, without revealing any information regarding the program, the data and the results, according to which the instructions of the program are simulated using SUBLEQ instructions and the execution of the program is divided among a plurality of participating computational resources such as one or more clouds, which do not communicate with each other, while secret sharing all the program's SUBLEQ instructions, to hide their nature of operation and the sequence of operations. Private string matching is secretly performed by comparing strings represented in secret shares, for ensuring the execution of the right instruction sequence. Then arithmetic operations are performed over secret shared bits and branch operations are performed according to the secret shared sign bit of the result.

A method of providing a distributed scheme for executing a RAM program, without revealing any information regarding the program, the data and the results, according to which the instructions of the program are simulated using SUBLEQ instructions and the execution of the program is divided among a plurality of participating computational resources such as one or more clouds, which do not communicate with each other, while secret sharing all the program's SUBLEQ instructions, to hide their nature of operation and the sequence of operations. Private string matching is secretly performed by comparing strings represented in secret shares, for ensuring the execution of the right instruction sequence. Then arithmetic operations are performed over secret shared bits and branch operations are performed according to the secret shared sign bit of the result.

An integrated circuit includes a first memory cell array and a controller. The first memory cell array includes a first array of volatile memory cells having a first retention data time. The controller is coupled to the first memory cell array. The controller is configured to write data to each memory cell in the first memory cell array in response to the integrated circuit being successfully logged into, read data from each memory cell in the first memory cell array in response to the integrated circuit being powered on, and determine whether to allow an authentication operation of the integrated circuit in response to reading data from each memory cell in the first memory cell array.

A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

Embodiments described herein include a system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for delay-based physical unclonable functions (PUFs) for chiplets to verify system integrity. A die may include a plurality of chiplets including a first chiplet and a second chiplet. The first chiplet may be connected to the second chiplet via an interposer. As part of an authentication process, the first chiplet may request the second chiplet to transmit a signal via one or more wires of the interposer. A first signature based on the characteristics of the transmitted signal may be measured at a first time, which constitutes the first evaluation of the PUF. The first signature may be used as a baseline comparison for subsequent signatures as a means to confirm that the chiplets, interposers, and/or interconnects have not been altered or modified.

Embodiments described herein include a system, apparatus, article of manufacture, method and/or computer program product embodiments, and/or combinations and sub-combinations thereof, for delay-based physical unclonable functions (PUFs) for chiplets to verify system integrity. A die may include a plurality of chiplets including a first chiplet and a second chiplet. The first chiplet may be connected to the second chiplet via an interposer. As part of an authentication process, the first chiplet may request the second chiplet to transmit a signal via one or more wires of the interposer. A first signature based on the characteristics of the transmitted signal may be measured at a first time, which constitutes the first evaluation of the PUF. The first signature may be used as a baseline comparison for subsequent signatures as a means to confirm that the chiplets, interposers, and/or interconnects have not been altered or modified.

A method for detecting perturbations in a logic circuit including a plurality of datapaths coordinated by a clock signal and at least one test circuit having a programmable length datapath for varying a test propagation delay. The test circuit further including inputs, an output and an error generator for providing an error in case that the output is different than an expected output for the inputs. The test circuit having a calibration mode including determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error, adjusting the programmable length datapath to include therein a tolerance delay, and switching into a detection mode configured to detect a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error.

A method for detecting perturbations in a logic circuit including a plurality of datapaths coordinated by a clock signal and at least one test circuit having a programmable length datapath for varying a test propagation delay. The test circuit further including inputs, an output and an error generator for providing an error in case that the output is different than an expected output for the inputs. The test circuit having a calibration mode including determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error, adjusting the programmable length datapath to include therein a tolerance delay, and switching into a detection mode configured to detect a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error.