The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single types of substrates in multiple types of cleanspace environments particularly to form hardware based encryption devices and hardware based encryption equipped communication devices and multi-chip modules such as chiplets. In some embodiments, a collocated composite cleanspace fabricator may be capable of processing semiconductor devices into integrated circuits and then performing assembly operations to result in product in packaged form. Customized smart devices, smart phones and touchscreen devices may be fabricated in examples of a cleanspace fabricator. The assembly processing may include steps to form hardware based encryption.

The present invention provides various aspects for processing multiple types of substrates within cleanspace fabricators or for processing multiple or single types of substrates in multiple types of cleanspace environments particularly to form hardware based encryption devices and hardware based encryption equipped communication devices and multi-chip modules such as chiplets. In some embodiments, a collocated composite cleanspace fabricator may be capable of processing semiconductor devices into integrated circuits and then performing assembly operations to result in product in packaged form. Customized smart devices, smart phones and touchscreen devices may be fabricated in examples of a cleanspace fabricator. The assembly processing may include steps to form hardware based encryption.

An integrated circuit includes a number of components disposed at a surface of a semiconductor body and an interconnect region connecting the components into a functional circuit. A metallic shield is also produced in the interconnect region. A configurable stage is configurable to operate in a receiving antenna configuration or in a detection configuration during which the integrated circuit is configured to detect a presence of an external electromagnetic radiation representative of an attack by injection of faults

An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

A dynamic transaction card that is manufactured using conductive plastic jumpers that will dissolve when in contact with a solvent used to tamper with the dynamic transaction card. Internal components of a dynamic transaction card may be manufactured using a synthetic or semi-synthetic organic material, such as, for example, plastics. These materials may be conductive to provide functionality to a dynamic transaction card, such as a connection between an integrated circuit and other card components such that when the materials dissolve, the connections are broken and the dynamic transaction card may be inactive due to the loss of various connections.

An integrated circuit device includes a semiconductor substrate layer and at least one active layer including electronic components and supported by the semiconductor substrate layer. The semiconductor substrate layer and the at least one active layer are sandwiched between two protective layers acting as physical obstacles to prevent the passage of radiations. In addition, the two protective layers are electrically connected to a detection circuit that can monitor an electrical information of the protective layers and detect a physical attack of at least one of the two protective layers, based on the monitored electrical information.

A protected circuit is provided comprising multiple essentially identical circuits, such as TPM (Trusted Platform Module) hosted in a common chip-housing, such that the signals thereof interfere with each other and it is difficult to obtain information therefrom. Additional protection may be achieved by adding a random delay to mask any relation between contents of processed information packages and the processing time required between in- and output signals of protected circuits. A physical barrier may be provided in order to prevent or at least limit physical access to for example at least one TPM chip arranged inside of the barrier. The physical barrier may comprises an impedance, i.e. in form of a capacitor with capacity C and or resistor R and or inductivity L, for example formed by two of the reflector layers with an absorbing material in between. Any impedance (i.e. capacity C and/or resistance R and/or inductivity L) change can be detected and any impedance (i.e. capacity and/or resistance and/or inductivity L) change beyond a chosen threshold is indicative of an attempt to physically destruct or enter the barrier. Upon detecting an impedance (i.e. capacity C and/or resistance R and/or inductivity L) change beyond the threshold, any suitable action may be performed, such as deleting all information from the chip, destroying the chip or providing wrong information. The barrier may also act as a reflector for reflecting the desired signal of the at least one chip, such that the desired signal and the reflected signals interfere with each other and it is difficult to obtain information therefrom.

A protected circuit is provided comprising multiple essentially identical circuits, such as TPM (Trusted Platform Module) hosted in a common chip-housing, such that the signals thereof interfere with each other and it is difficult to obtain information therefrom. Additional protection may be achieved by adding a random delay to mask any relation between contents of processed information packages and the processing time required between in- and output signals of protected circuits. A physical barrier may be provided in order to prevent or at least limit physical access to for example at least one TPM chip arranged inside of the barrier. The physical barrier may comprises an impedance, i.e. in form of a capacitor with capacity C and or resistor R and or inductivity L, for example formed by two of the reflector layers with an absorbing material in between. Any impedance (i.e. capacity C and/or resistance R and/or inductivity L) change can be detected and any impedance (i.e. capacity and/or resistance and/or inductivity L) change beyond a chosen threshold is indicative of an attempt to physically destruct or enter the barrier. Upon detecting an impedance (i.e. capacity C and/or resistance R and/or inductivity L) change beyond the threshold, any suitable action may be performed, such as deleting all information from the chip, destroying the chip or providing wrong information. The barrier may also act as a reflector for reflecting the desired signal of the at least one chip, such that the desired signal and the reflected signals interfere with each other and it is difficult to obtain information therefrom.

Circuits are protected from timing attacks by adding a random delay to mask any relation between contents of processed information packages and the processing time required between in- and output signals of protected circuits. This random delay has to be performed preferably inside the protected volume and can be realized by one or more random delay buffers that are realized by means of e.g. random shift-registers. Further protection may be provided by situating the circuits in a single chip housing, such that the signals thereof interfere with each other and it is difficult to obtain information therefrom. A physical barrier may be provided in order to prevent or at least limit physical access to for example at least one TPM chip arranged inside of the barrier. The physical barrier comprises an impedance, i.e. in form of a capacitor with capacity C and or resistor R and or inductivity L, for example formed by two of the reflector layers of the barrier with an absorbing material in between. Any impedance (i.e. capacity C and/or resistance R and/or inductivity L) change can be detected and any impedance (i.e. capacity and/or resistance and/or inductivity L) change beyond a chosen threshold is indicative of an attempt to physically destruct or enter the barrier. Upon detecting an impedance (i.e. capacity C and/or resistance R and/or inductivity L) change beyond the threshold, any suitable action may be performed, such as deleting all information from the chip, destroying the chip or providing wrong information. The barrier may also act as a reflector for reflecting the desired signal of the at least one chip, such that the desired signal and the reflected signals interfere with each other and it is difficult to obtain information therefrom.