Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.

A method of designing a fire suppression system including: determining nozzle placement for nozzles of a fire suppression system within a location; determining piping placement for pipes of the fire suppression system within the location; determining whether the nozzle placement or piping placement violate a constraint; and generating a map displaying the nozzle placement and the piping placement on a computing device.

A system for designing a circuitry configuration of heat-exchanger units includes an interface to acquire design parameters the heat-exchanger units, a memory to store computer-executable programs including a relaxed decision diagram formation module, and a processor, in connection with the memory, configured to perform the computer-executable programs. The computer-executable programs include steps of providing a configuration of the heat-exchanger units, providing the design parameters of the heat-exchanger units acquired via the interface, generating a relaxed decision diagram based on the design parameters, creating constraints with respect to connections of the heat-exchanger units according to the relaxed decision diagram, and generating feasible configurations of the heat-exchanger units by a mixed-integer-programing method using the constraints.

Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Routing a circuit path includes selecting pixels on the circuit path based at least on penalty values associated with the pixels. Pixels on a rejected circuit path are penalized by increasing their penalty values. Re-routing a rejected circuit path allows for pixels on previously rejected paths to be considered when rerouting the rejected circuit path, rather than being eliminated outright.

Systems and methods for creating a geometric design definition for 3D models designed to fit physical or digital template objects is disclosed. The 3D models can transform to fit specific physical or digital objects which are different from but topologically isomorphic to the original template objects based on visual or mathematical inputs. To validate the fit, the generated 3D model can be compared with the specific physical or digital objects for which the 3D model is generated to fit, and the geometry of generated 3D model can be adjusted to improve the fit if the generated 3D model is not validated. The accuracy of the fit of the generated 3D models can be improved iteratively.

A method for generating a path for wire arc additive manufacturing is provided in this disclosure, which relates to the technical field of additive manufacturing, and includes following steps: generating a model in which a three-dimensional model is established according to angle constraint of the wire arc additive manufacturing; layering the model in which the three-dimensional model is layered along a height direction; selecting discrete points in which a plurality of discrete points are selected according to curve curvature for different layers of the model; obtaining coordinates of the discrete points; determining a printing direction; obtaining coordinates of the discrete points and corresponding printing directions; and generating a control program. The method according to the disclosure is simple, has a wide application range, can satisfy printing of complex shapes, and can serve to well form for structures with maximum printing inclination of 60 degrees, thus improving forming effect of printing.

A power intent may be loaded on an integrated circuit (IC) design, where the power intent may be represented by a set of constraints. A logic network may be constructed based on the set of constraints and a rule check which is desired to be performed on the power intent. In response to a failure of the rule check, one or more refutation proofs may be created based on the logic network. A subset of the set of constraints may be identified based on the one or more refutation proofs, where the subset of the set of constraints may include an inconsistency which caused the rule check to fail.

Tools and techniques are described to automate line testing when wiring devices (such as equipment and sensors) to controllers. Controllers have access to databases of the devices that are controlled by them, including wiring diagrams and protocols, such that the controller can automatically check that each wire responds correctly to stimulus from the controller. After testing, a reporting device rapidly shows the results of the line testing.

A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.