Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.

The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

A method for producing an experimental output satisfying an objective includes conducting an experimental execution process including applying a selection criterion to select an approach to determining a set of parameters for a set of experiments, and determining a first set of parameters for a first experiment according to the selected approach based on one or more of (i) a predicted relationship between a set of parameters and a characteristic of a corresponding experimental output, (ii) the measured characteristic of a second experimental output from a second experiment executed according to a second set of parameters, (iii) the objective, and (iv) a parameter selection rule. Conducting an experimental execution process includes controlling execution of the first set of experiments according to the first set of parameters, where execution of each first experiment includes conducting the experiment according to the first set of parameters to produce a first experimental output; and measuring the characteristic of the first experimental output. The method includes determining whether the objective is satisfied by the experimental execution process, and, when the objective is not satisfied by the experimental execution process, conducting a subsequent experimental execution process.

A computer-readable storage medium that stores computer program code which, when executed by one or more processors, causes the one or more processors to execute tools for designing an integrated circuit (IC). The tools include a placing and routing tool that generates layout data and wire data corresponding to a net included in the IC by placing and routing standard cells defining the IC, the wire data including physical information of a wire implementing the net, and a timing analysis tool that calculates a wire delay with respect to the wire corresponding to the net, based on the physical information, updates the wire delay based on process variation of the wire, and calculates a timing slack by using the updated wire delay.

An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

A constraint graph for a candidate routing solution is created; each node in the graph represents a position of an end of a metal shape and each arc in the graph represents a design rule constraint between two of the nodes. A solution graph is computed, for at least a portion of the constraint graph, using a shape processing algorithm. The solution graph is checked for design rule violations to generate one or more violation graphs. A constraint window and a selection of one or more arcs for at least one of the violation graphs are generated. The candidate routing solution is revised, based on one or more violated design rules corresponding to at least one of the selected arcs within the constraint window. Optionally, an integrated circuit is fabricated in accordance with the revised solution.

The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

Predicting performance of a circuit design includes determining memory access patterns of kernels of the circuit design for implementation in an integrated circuit (IC) and generating a plurality of different floorplans. Each floorplan specifies a mapping of memory interfaces of the kernels to memories of the selected IC and an allocation of the kernels to a plurality of programmable pattern generator (PPG) circuit blocks of a circuit architecture implemented in the IC. The plurality of different floorplans are executed using the circuit architecture in the IC. The plurality of PPG circuit blocks mimic the memory access patterns of the kernels for each of the plurality of different floorplans during the executing. One or more design constraints are generated based on a selected floorplan. The selected floorplan is selected from the plurality of different floorplans based on one or more performance metrics determined from the executing.

Processes for optimizing the geometry of a blade for use in a propeller are disclosed. In one exemplary process, an optimization routine that generates new blade geometries based on structural parameters and calculates performance parameters of each blade geometry, including aerodynamic performance parameters, farfield acoustic parameters, and/or electrical power requirements to operate a propeller having the blade geometry, is performed. The optimization routine receives design parameters and weightings from a user and can use one or more surrogate algorithms to map a design space of the weighted values of the design parameters to find their local minima. The optimization routine then determines an optimized blade geometry using a gradient-based algorithm to generate new blade geometries to explore the minima until the weighted values of the design parameters converge at an optimized blade geometry representing the global minima of the design space.