The present invention discloses an ejector pin device for chip packaging, which comprises a pin cylinder, a base and an ejector pin base module, wherein the pin cylinder sleeves the ejector pin base module, the base is located below the ejector pin base module and is configured to fix the ejector pin base module; and the ejector pin base module comprises a knob unit and a supporting unit. An effect of adjusting the knob unit can be acted on the corresponding supporting unit, so that the requirements of the numbers and positions of the ejector pins required by different products are satisfied and metal foreign matters are reduced, thereby improving the efficiency of replacing products by a worker.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

A method for modeling a serializer/deserializer (SerDes) model includes generating plural data sets including noise simulation data of the SerDes model and output measurement data of an actual SerDes, training a machine learning model based on the plural data sets, and applying the trained machine learning model and an estimation model to a model included in the SerDes model. The estimation model provides the noise simulation data as an input to the trained machine learning model.

An automatic layout method for a pad ring used for optimizing the electrostatic discharging capacity of a chip, comprising: determining, on the basis of information of a selected process library and of package constraint information, the types and number of signal lead modules of a chip, and combined with designed total power consumption data, determining the types of power supply lead modules and a basic required number corresponding to each type of power supply lead modules; producing, on the basis of the types and the numbers of the signal lead modules and of that of the power supply lead modules and of the package constraint information, groups of lead modules to be laid out respectively for four boundaries; executing a first automatic layout with respect to each boundary, when a first boundary module is inserted, sequentially polling and calling a second subprogram and a third subprogram, respectively used for inserting the signal lead modules, a first power supply lead modules and/or a second power supply lead module; and executing a second automatic layout on the basis of the size of a remaining gap when the first automatic layout is executed. This is used for optimizing the electrostatic discharging capacity of the chip.

A layout method is configured to design a layout of a bridging circuit between source circuit and a destination circuit of a circuit system. The layout method includes: categorizing the bridging circuit into sub-regions according to physical structural characteristics; obtaining default sub-region model units corresponding to the sub-regions from a database; setting the default sub-region model units by the parameters to obtain sub-region models; extracting, using an electromagnetic simulation software, electrical models from the sub-region models, respectively; connecting the sub-region models to obtain, using a circuit simulation software an entire electrical model; evaluating whether the entire electrical model meets a specific requirement of the bridging circuit with respect to the circuit system; and when the entire electrical model meets the specific requirement, obtaining a layout rule according to the sub-region models.

A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

Systems and methods are disclosed for integrated circuit design using integrated circuit shells. For example, a system may generate an integrated circuit core design expressed in a hardware description language. The integrated circuit core design may express circuitry that describes one or more functions to be included in an application specific integrated circuit (ASIC). The one or more functions may have connection points providing first inputs and outputs to the one or more functions. The system may query an integrated circuit shell expressed in a hardware description language. The integrated circuit shell may express circuitry that describes a limited set of pads to be implemented in the ASIC. The limited set of pads may provide second inputs and outputs to the integrated circuit. The query may determine availability of pads of the limited set of pads to connect to the connection points of the one or more functions.

The present disclosure relates to an innovative method of assigning signals to general-purpose input/output pads of an integrated circuit chip. An inductance matrix for the input/output pads is obtained. A candidate assignment is made of a differential signal to a pair of the input/output pads, and a differential mutual inductance is determined for each open pad location in relation to the pair of input/output pads. Single-ended signals are assigned to open pad locations having the lowest differential mutual inductances. The jitter contribution due to each assigned single-ended signal is computed, and a total jitter is updated. In a first embodiment, said assigning, computing and updating steps are repeated until the total jitter exceeds a total jitter budget. In a second embodiment, said assigning, computing and updating steps are repeated until a number of assigned single-ended signals is equal to a target number. Other embodiments and features are also disclosed.

The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Various embodiments are directed to analysis of three-dimensional structure of an integrated circuit (IC) sample in order to enable sample preparation for physical inspection and hardware assurance. Specifically, various embodiments provide a structural analysis framework that enables high-quality sample preparation, including careful material removal of IC packaging material without damaging internal components of the IC sample. In various embodiments, the structural analysis framework involves receiving a digital twin model of an IC sample, and the digital twin model may be generated using X-ray CT imaging. Then, various regions of interest of the IC sample may be identified and selected via the digital twin model. The structural analysis framework further includes performing THz-TDS to collect ultra-high-resolution thickness information at the regions of interest. Both the digital twin model and the ultra-high-resolution thickness information may then be used to guide material removal of the IC sample.