Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Embodiments include predictive antenna diode insertion. Aspects of the invention include obtaining a design of a macro, the design including an internal pin disposed on a first layer of the macro. Aspects of the invention also include determining a length of a wire needed to connect the internal pin to a furthest edge of the macro for each of two layers above the layer the internal pin. Aspects of the invention further include adding, to the design of the macro, an antenna diode to the internal pin based on the determination that an area of the wire needed exceeds a threshold value, wherein the area of the wire is based on the length and a width of the wire.

A method for analyzing a specification parameter of an electronic component includes inputting a package type and at least one engineering drawing image of an electronic component; acquiring a probability value that in each view of the different viewing directions each of the plurality of specification parameter of the electronic component is labeled; taking the view of each of the plurality of specification parameters in the view direction with a highest probability value as a recommended view; performing a box selection on the plurality of specification parameters for at least one engineering drawing image with the same viewing direction as that of the recommended view by an object detection model; and identifying box-selected specification parameters to acquire a size value of identified specification parameters from the at least one engineering drawing image, and converting the size value into a corresponding editable text for output.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a device may receive layout information that identifies a configuration of an antenna array of antennas, wherein the antenna array is to include a plurality of antenna subarrays and a plurality of antenna chips, wherein each antenna chip is communicatively coupled to antennas of an associated antenna subarray; determine, based at least in part on a phase shift characteristic associated with the antennas, a set of phase differences between antenna subarrays; determine, based at least in part on the set of phase differences, a chip position of each antenna chip relative to the associated antenna subarray; and generate, based at least in part on the chip position of each antenna chip, a layout of an antenna package to receive the antenna array and the plurality of antenna chips. Numerous other aspects are provided.

The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.

The present disclosure provides a method of measuring a plurality of voids in an underfill material of an underfill package. The method includes operations of obtaining a welding angle profile of the underfill package; obtaining a simulated void profile of the underfill package according to the welding angle profile; determining a plurality of high-risk void regions according to the simulated void profile; simulating, according to a selected pressure and a selected temperature of the underfill material, a first high-risk void region of the plurality of high-risk void regions to generate an updated void profile; and determining whether the updated void profile meets a void requirement of the underfill package.

A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

An evaluation apparatus includes a processor that performs operations including reading a simulation parameter of a topography simulator and first range information or second range information that are associated with each other, the simulation parameter being calculated to cause the topography simulator output topography information of a processed target object that is to be obtained by processing the unprocessed target object under a predetermined processing condition, providing topography information of a new unprocessed target object and the simulation parameter to the topography simulator to cause the topography simulator to predict topography information of a new processed target object that is processed under the predetermined processing condition, and outputting a result of comparing the topography information of the new unprocessed target object with the first range information or a result of comparing the topography information of the new processed target object with the second range information.

A method of performing an electro-thermo simulation includes defining a non-linear heat diffusion problem for at least a portion of a semiconductor device to be modeled, performing a finite volume discretization of the non-linear heat diffusion problem, reformulating a non-linear term of the discretized non-linear heat diffusion problem to decrease dimensions thereof, performing a hyper reduction of the reformulated non-linear term, and recovering the non-linear heat diffusion problem for the portion of the semiconductor device, and manufacturing the modeled semiconductor device.

Systems and methods are provided for a turnkey modular printed circuit board enclosure that is generated using a template generator. The template generator accepts a user input comprising an enclosure parameter, based on which a manufacturing file may be generated. The manufacturing file may be provided to a fabricator for fabricating the enclosure or the manufacturing file may be modified in a printed circuit board design environment to incorporate a printed circuit board into the enclosure. The printed circuit board may be a separate printed circuit board that is inserted into the enclosure or it may be embedded in a face of the enclosure.