The present disclosure provides systems and methods for automatic packaging determination comprising memory storing instructions and at least one processor performing steps comprising: receiving an order comprising at least one item; searching at least one data store to determine tags and properties associated with each item; sorting the items into at least one group; for each group: performing an optimization process for packaging the items in the group, by: selecting a data structure representing a first package; iteratively simulating packaging of a largest item of the group into the first package until all items are packaged, wherein if the simulating determines that the items in the group do not fit into the selected package: choosing a larger package, iteratively packing until all items are packed in the larger package; and generating set of instructions for packaging the items into the box; and sending the generated instructions for display.

According to one embodiment, a method, computer system, and computer program product for determining packaging compatibility is provided. The embodiment may include creating a digital twin representation of a manufacturing object based on received data of the manufacturing object. The embodiment may include identifying a position of the digital twin representation within a hierarchy of associated digital twin representations. The embodiment may include monitoring for a change to the digital twin representation. The embodiment may include determining a compatibility of a changed digital twin representation within the hierarchy. In response to determining that the changed digital twin representation is incompatible within the hierarchy, the embodiment may include sending an incompatible change alert.

The present disclosure relates to a computer-implemented method for use in an electronic design. Embodiments may include performing, using a processor, a simulation of a multi-layered electronic structure and extracting a circuit model of the multi-layered electronic structure, wherein the circuit model includes at least two plates. Embodiments may also include extracting one or more parasitic parameters of at least one via associated with the circuit model and calculating a coupling coefficient associated with a controlled source of the circuit model. Embodiments may further include extracting a transmission line mode from the circuit model and linking the circuit model, at least one via, and the transmission line mode to an external circuit to generate a modeled system. Embodiments may also include solving the modeled system using a modified nodal analysis.

A method of designing a package configured to securely accommodate one of two or more differently shaped objects. The method comprises: establishing a predetermined orientation for each of the two or more differently shaped objects relative to common axes; identifying dimensionally common points of the two or more differently shaped objects; and developing a design for a package configured to constrain the two or more differently shaped objects at the identified dimensionally common points.

Methods and systems for generating a product packaging model for a product offering of a set of product items associated with a merchant account. At an e-commerce platform, a trigger event is detected and, in response, two or more product items are automatically selected to form a kit that makes up the product offering. Model data for the two or more product items and packaging parameters are used to automatically select a packaging option and to build a product packaging model that is sent to the merchant account. The product packaging model may be a three-dimensional computer model of the kit containing the two or more product items.

Embodiments include a computer implemented method comprising: while designing a chip, identifying a plurality of partitions in the chip, for a first partition of the plurality of partitions in the chip, identifying a plurality of pins configured to interconnect the first partition with one or more other partitions of the plurality of partitions of the chip, assigning a name to each of the plurality of pins associated with the first partition of the plurality of partitions, based on the names assigned to each of the plurality of pins, forming a plurality of groups such that each group of the plurality of groups is associated with a corresponding one or more pins of the plurality of pins, and based on forming the plurality of groups, designing a first subset of the plurality of pins to be located at close proximity in the chip.

Systems and methods are provided for efficient box packing and visualization. One method comprises receiving, from a remote system, an order comprising at least one item; searching at least one data store to determine dimensions associated with the at least one item; and modifying dimensions of at least one largest item of the order using a factor. The method may further comprise selecting a data structure representing a first package, the data structure comprising a size of the first package; iteratively simulating packing the items into the first package based on the modified dimensions, until all items are packed in the selected package; and generating at least one set of instructions for packing the items into the selected package. The method may further comprise sending the generated instructions to a second system for display, the instructions including at least one item identifier and one package identifier.

A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.

A semiconductor device includes: first and second core regions; first and second input/output (I/O) regions coupled to each other and to the first and second core regions; the first and second I/O regions being between an expendable region and correspondingly the first and second core regions; a sealing ring surrounding the core regions and the I/O regions; metallization layers and interconnection layers; inter-communication (inter-com) segments extending between the I/O regions; first and second parapets which extend from the first to third sides of the sealing ring or from first to second locations on corresponding third and fourth parapets, the latter extending from the first to third sides of the sealing ring; the first parapet being between the first core region and the first I/O region; and the second parapet being between the second core region and the second I/O region.

A method for determining a housing capable of accommodating waste heat generating electronic components on a printed circuit board includes: detecting an arrangement of the electronic components on a mounting side of the printed circuit board; determining several functional areas within the mounting side in which at least one of the electronic components is arranged according to the detected arrangement; assigning a thermal function to each of the functional areas, each of the thermal functions comprising: a function for generating waste heat due to a power dissipation of the at least one electronic component arranged in a respective functional area according to the detected arrangement during operation, and a maximum temperature up to which the at least one electronic component arranged in the respective functional area is operable without damage and performance limitation.