Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.

Methods and systems for IC photomask patterning are described. In some embodiments, a method includes inserting a dummy region in an IC design layout, the IC design layout includes an active region, and the active region and the dummy region is separated by a first distance. The method further includes performing one or more operations on the IC design layout, and the active region and the dummy region is separated by a second distance substantially less than the first distance. The method further includes performing a dummy region size reduction on the IC design layout to increase the second distance to a third distance substantially greater than the second distance, and the third distance is substantially greater than a minimum feature size to be patterned by a photolithography tool. The method further includes forming a photomask using the IC design layout.

A system enhances a system design to incorporate safety measures. The system receives a system design for processing through various stages of design using design tools, for example electronic design automation tools for introducing safety features in a circuit design. The system receives safety requirements for the system design, the safety requirements specifying safety measures for the system design. The system generates from the safety requirements, a safety specification storing a set of commands. The system generates a system design enhanced with safety measures. The enhanced system design it generated for at least a subset of the plurality of tools. A tool processes the generated safety specification to implement safety measures in the system design according to the received safety requirements.

Integrated circuits (IC) are provided. An IC includes a plurality of macros and a top channel. Each macro includes a macro boundary and a main pattern surrounded by the macro boundary. The top channel includes a plurality of first and second sub-channels. Each first sub-channel is arranged between a first macro and a second macro, and is formed by a plurality of first dummy boundary cells. Each second sub-channel is arranged between two of the second macros, and is formed by a plurality of second dummy boundary cells. The macro boundaries of the first macros are formed by the first dummy boundary cells, and the macro boundaries of the second macros are formed by the second dummy boundary cells. A first gate length of dummy patterns within the first dummy boundary cells is greater than a second gate length of dummy patterns within the second dummy boundary cells.

One embodiment provides a method and a system for generating test vectors for testing a computational system. During operation, the system obtains a design of the computational system, the design comprising an original system. The system generates a design of a fault-augmented system block by adding a plurality of fault-emulating subsystems to the original system; generates a design of an equivalence-checking system based on the original system and the fault-augmented system block; encodes the design of the equivalence-checking system into a logic formula, with variables within the logic formula comprising inputs and outputs of the original system and inputs and outputs of the fault-augmented system block; and solves the logic formula to obtain a test vector used for testing at least one fault in the computational system.

Methods, apparatus, systems and articles of manufacture are disclosed to simulate metastability for circuit design verification. An example apparatus includes an input handler to receive circuit design data indicative of a circuit design, a circuit modeler to generate a simulation model based on the circuit design data, a simulator to simulate operation of the circuit design based on the simulation model, a metastability injector to insert metastability logic into the simulation model during the simulation, and a metastability controller to control the metastability logic during the simulation.

Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

A JTAG-based burning device, comprising controllable switches provided between a TDI end of a JTAG host (1) and a first chip and between every two adjacent chips, and further comprising a main controllable switch module (2) provided between each chip and a TDO end of the JTAG host (1). According to a received burning instruction, the JTAG host (1) can control an input end of a corresponding controllable switch to be connected to a corresponding output end thereof, and also control an output end of the main controllable switch module (2) to be connected to a corresponding input end thereof. Hence, the device merely needs to build a circuit to automatically adjust a JTAG link by controlling the connection relationship between the input end and the output end of the corresponding switch, achieving burning of the firmware of different chips or a combination of chips, without manual adjustment, thereby improving the test efficiency, and simplifying a circuit structure.

A Register Transfer Level (RTL) representation is recovered from a netlist representing an integrated circuit (IC). The netlist is converted to a graph comprising nodes belonging to a set of node types and edges connecting the nodes. The set of node types includes an instance node type representing an electronic component and a wire node type representing signal transfer between components. The graph is converted to a standardized graph by replacing subgraphs of the graph with standardized subgraphs. An RTL representation of the standardized graph is generated by operations including building signal declarations in a hardware description language (HDL) from the wire nodes of the standardized graph and building signal assignments in the HDL from instance nodes of the standardized graph.

Out-of-bounds recovery circuits configured to detect an out-of-bounds violation in an electronic device, and cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation is detected. The out-of-bounds recovery circuits include detection logic configured to detect that an out-of-bounds violation has occurred when a processing element of the electronic device has fetched an instruction from an unallowable memory address range for the current operating state of the electronic device; and transition logic configured to cause the electronic device to transition to a predetermined safe state when an out-of-bounds violation has been detected by the detection logic.