A simulator can simulate a circuit design describing an electronic device using a single processing device of a computing system. The simulator can generate profile data associated with compilation of the circuit design and the single processing device simulation of the compiled circuit design. The profile data can identify multiple different ways to partition the circuit design and include information corresponding to the single processing device simulation of the compiled circuit design. A parallel simulation qualifier can determine a parallelism factor corresponding to an expected performance of the computing system in a multiple processing device simulation of the circuit design based on the profile data from the single processing device simulation of the circuit design. The simulator can utilize the parallelism factor to partition the circuit design in one of the different ways, and simulate the partitioned circuit design with multiple processing devices of the computing system.

Hardware-software interaction testing is performed using formal verification for language-specified hardware designs. A description of valid access using an interface for a configuration space of a language specified hardware design and a description of a valid output of the language-specified hardware design is received. Formal verification is performed on the language-specified hardware design using the interface for the configuration space according to the description of valid access using the interface. A sequence of access to the configuration space using the interface that causes a failure to produce the valid output of the language-specified hardware design according to the description of valid output to identify as an error for the language-specified hardware design.

Implementing a design for a heterogeneous device can include mapping, using computer hardware, a plurality of applications of a design for a device to a plurality of domains of the device, wherein each domain includes a different compute unit, performing, using the computer hardware, validity checking on the plurality of applications, detecting, using the computer hardware, a conflict between two or more of the plurality of applications from the validity checking, and, in response to the detecting, generating a notification of the conflict using the computer hardware. Operations such as automatically generating a boot image, debugging, and/or performing system level performance analysis may also be performed.

The present disclosure discloses a model-based architecture design method for an unmanned aerial vehicle (UAV) system, which aims to deal with challenges of changeable operational requirements, shortened design period, and decreased technical risks in a current UAS design process. A data-driven architecture development method is used. By establishing an architecture development framework of the UAS, a framework modeling process oriented to different viewpoints is designed, and modeling and simulation specifications based on SysML and Modelica are defined, such that design of the UAS starts from conception and confirmation of an operational concept. The method focuses on forward analysis and design of a system framework, and concept verification and metric closed-loop are carried out at an early stage of the design of the UAS by virtue of logic modeling and system simulation.

A development system and a method of an offline software-in-the-loop simulation are disclosed. A common firmware architecture generates a chip control program. The common firmware architecture has an application layer and a hardware abstraction layer. The application layer has a configuration header file and a product program. A processing program required by a peripheral module is added to the hardware abstraction layer during compiling. The chip control program is provided to a controller chip or a circuit simulation software to be executed to control the product-related circuit through controlling the peripheral module.

A method for providing a real-time-capable simulation for control unit development, wherein the real-time-capable simulation simulates a control unit or an environment of a control unit or a combination of a control unit and an environment of the control unit. The real-time-capable simulation has a co-simulation of a real-time-capable sub-simulation and a non-real-time-capable sub-simulation that interacts with the real-time-capable sub-simulation, wherein the real-time-capable sub-simulation and the non-real-time-capable sub-simulation are designed for communication of simulation data. The real-time-capable sub-simulation has a first simulation time corresponding to real time and the non-real-time-capable sub-simulation has a virtual, second simulation time that is coupled to the first simulation time and that matches the first simulation time at the start of the real-time-capable simulation.

Provided is a method for analyzing and designing a physical system architecture of a safety-critical system, wherein a physical system analysis model representing the physical system architecture of the safety-critical system is modified incrementally until calculated failure rates of failure modes of the physical system analysis model are less or equal to failure rates of corresponding failure modes of a functional system analysis model representing a functional system architecture of the safety-critical system.

Example implementations involve systems and methods which can involve storing interface (I/F) communication activity records of a plurality of simulation engines during execution of a co-simulation, and for a subsequent execution of the co-simulation, replacing one or more of the plurality of simulation engines with a simulation engine repeater configured to reproduce I/F communication activity from the stored I/F communication activity records corresponding to the replaced one or more of the plurality of simulation engines during the subsequent execution of the co-simulation and to log a real time consumed for execution of the reproduced I/F communication activity in the subsequent execution and a simulation time consumed for execution of the reproduced I/F communication activity for each simulation step, the real time determined based on a real time difference between a start of each simulation step and completion of synchronization with a co-simulator bus at an end of each simulation step.

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.