The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.

Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

A variety of techniques are disclosed for customizing a digital model of an aesthetic housing to receive a functional component and an interface component for the functional component.

Embodiments of the invention provide systems and methods for nesting objects in 2D sheets and 3D volumes. In one embodiment, a nesting application simplifies the shapes of parts and performs a rigid body simulation of the parts dropping into a 2D sheet or 3D volume. In the rigid body simulation, parts begin from random initial positions on one or more sides and drop under the force of gravity into the 2D sheet or 3D volume until coming into contact with another part, a boundary, or the origin of the gravity. The parts may be dropped according to a particular order, such as alternating large and small parts. Further, the simulation may be translation- and/or position-only, meaning the parts do not rotate and/or do not have momentum, respectively. Tighter packing may be achieved by incorporating user inputs and simulating jittering of the parts using random forces.

A computer-implemented method for generating a color of an object displayed on a GUI. The method includes displaying on a graphical user interface a set of icons, each icon of the set being associated with a color, detecting a first user interaction on a first icon of the set, detecting a second user interaction that comprises at least a slide, modifying a value of a parameter of a first color associated with the first icon, the modification of the value being performed with the second user interaction, and computing a first new color that is the first color with the modified value of a parameter.

A method includes determining topographic information of a substrate for use in a lithographic imaging system, determining or estimating, based on the topographic information, imaging error information for a plurality of points in an image field of the lithographic imaging system, adapting a design for a patterning device based on the imaging error information. In an embodiment, a plurality of locations for metrology targets is optimized based on imaging error information for a plurality of points in an image field of a lithographic imaging system, wherein the optimizing involves minimizing a cost function that describes the imaging error information. In an embodiment, locations are weighted based on differences in imaging requirements across the image field.

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.