A method for facilitating data synchronization across a plurality of platforms is provided. The method includes retrieving a change event, the change event corresponding to an event stream from a first platform; parsing the change event to identify a record and a data operation; examining a synchronization database to determine whether a corresponding record is persisted in a database of a second platform; inserting the record into the synchronization database when the corresponding record is not persisted in the platform, the inserted record including a change indicator; and updating, by using the synchronization database, the database of the second platform to include the record.

The disclosed embodiments relate to securely booting firmware images. In one embodiment, a method is disclosed comprising receiving, by a memory device, a firmware update; validating, by the memory device, a signature associated with the firmware update; copying, by the memory device, an existing firmware image to an archive location, the archive location storing a plurality of firmware images sorted by version identifiers; booting, by the memory device, and executing the firmware update; and replacing, by the memory device, the firmware update with the existing firmware image stored in the archive location upon detecting an error while booting the firmware update.

There are provided systems and methods for a compute platform for machine leaning model roll-out. A service provider, such as an electronic transaction processor for digital transactions, may provide intelligent decision-making through decision services that execute machine learning models. When deploying or updating machine learning models in these engines and decision services, a model package may include multiple models, each of which may have an execution graph required for model execution. When models are tested from proper execution, the models may have non-performant compute items, such as model variables, that lead to improper execution and/or decision-making. A model deployer may determine and flag these compute items as non-performant and may cause these compute items to be skipped or excluded from execution. Further, the model deployer may utilize a pre-production computing environment to generate the execution graphs for the models prior to deployment or upgrading.

Methods, systems, and devices for reporting control information errors are described. A state of a memory array may be monitored during operation. After detecting an error (e.g., in received control information), the memory device may enter a first state (e.g., a locked state) and may indicate to a host device that an error was detected, the state of the memory array before the error was detected, and/or at least a portion of a control signal carrying the received control information. The host device may diagnose a cause of the error based on receiving the indication of the error and/or the copy of the control signal. After identifying and/or resolving the cause of the error, the host device may transmit one or more commands (e.g., unlocking the memory device and returning the memory array to the original state) based on receiving the original state from the memory device.

Selectively committing or rolling-back in-flight units of recovery is provided. An indicator is read in a transaction identifier information record corresponding to a unit of recovery that is in-flight. It is determined whether the indicator indicates a commit for the unit of recovery that is in-flight. In response determining that the indicator does indicate the commit for the unit of recovery that is in-flight, the unit of recovery that is in-flight corresponding to the transaction identifier information record is committed to form a committed unit of recovery. The committed unit of recovery corresponding to the transaction identifier information record is sent to a target system for further processing.

A memory system includes: a memory device; a first queue suitable for queuing commands received from a host; a second queue suitable for enqueuing the commands from the first queue and dequeuing the commands to the memory device according to the FIFO scheme; and a processor suitable for: delaying enqueuing a read command into the second queue until the program operation is successfully performed when a logical address of a write command, in response to which a program operation is being performed, is the same as a logical address corresponding to the read command enqueued in the first queue; and determining whether or not to enqueue a subsequent read command, which is enqueued in the first queue after the read command, into the second queue.

An embodiment relates to a computer-implemented data processing system and method for storing a data set at a plurality of data centers. The data centers and hosts within the data centers may, for example, be organized according to a multi-tiered ring arrangement. A hashing arrangement may be used to implement the ring arrangement to select the data centers and hosts where the writing and reading of the data sets occurs. Version histories may also be written and read at the hosts and may be used to evaluate causal relationships between the data sets after the reading occurs.

Various embodiments comprise systems and methods to maintain data consistency in a data pipeline. In some examples, a computing system comprises data monitoring circuitry that monitors the operations of the data pipeline. The data pipeline receives input data, processes the input data, and generates output data. The data monitoring circuitry receives and processes the output data sets to identify changes between the output data sets. The data monitoring circuitry generates a consistency score based on the changes that indicates a similarity level between the output data sets. The data monitoring circuitry determines when the consistency score exceeds a threshold value. When the consistency score exceeds the threshold value, the data monitoring circuitry generates and transfers an alert that indicates ones of the output data sets that exceeded the threshold value.

A system includes a multi-process application that runs. A multi-process application runs on primary hosts and is checkpointed by a checkpointer comprised of at least one of a kernel-mode checkpointer module and one or more user-space interceptors providing at least one of barrier synchronization, checkpointing thread, resource flushing, and an application virtualization space. Checkpoints may be written to storage and the application restored from said stored checkpoint at a later time. Checkpointing may be incremental using Page Table Entry (PTE) pages and Virtual Memory Areas (VMA) information. Checkpointing is transparent to the application and requires no modification to the application, operating system, networking stack or libraries. In an alternate embodiment the kernel-mode checkpointer is built into the kernel.

A memory device system includes: a first memory that has m lines of addresses and in which different pieces of data are respectively stored at the m lines of addresses, and a parity bit; a second memory that has m lines of addresses and in which same pieces of data as the pieces of data stored in the first memory are stored in an initial state; a first register that is connected with the first memory; a second register that is connected with the second memory; a comparator; a transfer register that stores the piece of data of the first memory; an error data register that stores the piece of data of the second register; an error address register that stores an address of the second memory; a parity calculation portion that calculates parity of all pieces of data; and a controller that performs a predetermined control.