G06F2201/845

VERIFYING PROCESSING LOGIC OF A GRAPHICS PROCESSING UNIT
20230043280 · 2023-02-09 ·

A method of verifying processing logic of a graphics processing unit receives a test task including a predefined set of instructions for execution on the graphics processing unit, the predefined set of instructions being configured to perform a predetermined set of operations on the graphics processing unit when executed for predefined input data. In a test phase, the test task is processed by executing the predefined set of instructions for the predefined input data first and second times at the graphics processing unit so as to, respectively, generate first and second outputs. A fault signal is raised if the first and second outputs do not match.

Storage system accommodating varying storage capacities
11714715 · 2023-08-01 · ·

A plurality of storage nodes in a single chassis is provided. The plurality of storage nodes in the single chassis is configured to communicate together as a storage cluster. Each of the plurality of storage nodes includes nonvolatile solid-state memory for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes such that the plurality of storage nodes maintain the ability to read the user data, using erasure coding, despite a loss of two of the plurality of storage nodes. A plurality of compute nodes is included in the single chassis, each of the plurality of compute nodes is configured to communicate with the plurality of storage nodes. A method for accessing user data in a plurality of storage nodes having nonvolatile solid-state memory is also provided.

CONFIGURABLE COMPUTER MEMORY
20230214228 · 2023-07-06 ·

A method for configuring a computer system memory, includes powering on the computer system; retrieving options for initializing the computer system; assigning to a first segment of the memory a first pre-defined setting; assigning to a second segment of the memory a second pre-defined setting; and booting the computer system.

Semiconductor device, control system, and control method of semiconductor device

A semiconductor device includes first and second CPUs, first and second SPUs for controlling a snoop operation, a controller supporting ASIL D of a functional safety standard and a memory. The controller sets permission of the snoop operation to the first and second SPUs when a software lock-step is not performed. The controller sets prohibition of the snoop operation to the first and second SPUs when the software lock-step is performed. The first CPU executes a first software for the software lock-step, and writes an execution result in a first area for the memory. The second CPU executes a second software for the software lock-step, and writes an execution result in a second area of the memory. The execution result written in the first area is compared with the execution result written in the second area.

Utilizing data source identifiers to obtain deduplication efficiency within a clustered storage environment

Described is a system (and method) that intelligently distributes data within a clustered storage environment. To provide such a capability, the system may distribute backup files by considering a source of the data to be backed-up. In particular, the system may leverage the ability of front-end components such as a backup application to perform a granular data source identification of data. Such information may be propagated to back-end components such as a storage filesystem in the form of a data source identifier (e.g. placement tag). The data source identifiers may then be accessed by the clustered storage system to intelligently distribute backup files amongst a set of storage nodes forming a cluster. For example, backup files from the same data source may be stored on the same storage node to obtain the same deduplication efficiency as a single storage system.

ENSURING HIGH AVAILABLITY OF REPLICATED DATABASE MANAGEMENT SYSTEMS DURING UPGRADES

An online system, such as a multi-tenant system ensures high availability of systems, for example, database management systems. The online system replicates the databases across multiple datacenters including: (1) a master node that receives read and write requests (2) a read-replica that receives only read requests and (3) a spare node that does not receive requests but acts as standby for high availability. One or more application servers may send read and write requests to the databases. The system performs a sweep of upgrades of the database nodes and also performs traffic quiescing of the requests received from the application servers to redirect the traffic across the database nodes as the upgrade sweep is orchestrated. The sweep of upgrades ensures that the availability of the database management system to the end users is maximized during the upgrade process.

System and method of dynamic system resource allocation for primary storage systems with virtualized embedded data protection

Embodiments provide for a primary storage array having multiple storage tiers. The multiple storage tiers include one or more performance tiers and at least one deduplicated storage tier storing deduplicated data. One embodiment provides for a data storage system including the storage array and an I/O engine to manage I/O requests for the storage array. The data storage system additionally includes a virtual execution environment to execute a virtual backup engine, the virtual backup engine to generate backup data for the one or more storage tiers of primary storage and deduplicate the backup data and a resource manager to manage a resource allocation to the virtual backup engine based on a hint received from the virtual backup engine, the hint associated with a backup operation that has a characterization selected from a set including computationally intensive and I/O intensive.

Error detection using vector processing circuitry

A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

DISTRIBUTION OF RESOURCES FOR A STORAGE SYSTEM
20230058369 · 2023-02-23 ·

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.

Configurable hyperconverged multi-tenant storage system

A method for managing processing power in a storage system is provided. The method includes providing a plurality of blades, each of a first subset having a storage node and storage memory, and each of a second, differing subset having a compute-only node. The method includes distributing authorities across the plurality of blades, to a plurality of nodes including at least one compute-only node, wherein each authority has ownership of a range of user data.