According to one general aspect, an apparatus may include a floating-point addition unit configured to generate a floating point result by either adding or subtracting two floating point operands together, wherein each floating point operand includes a mantissa portion and an exponent portion. The floating-point addition unit may include a mantissa shifting circuit configured to shift the mantissa portion of a smaller of the two floating point operands, and a sticky bit circuit configured to determine a sticky bit in parallel with the mantissa shifting circuit.