An engine architecture for processing finite automata includes a hyper non-deterministic automata (HNA) processor specialized for non-deterministic finite automata (NFA) processing. The HNA processor includes a plurality of super-clusters and an HNA scheduler. Each super-cluster includes a plurality of clusters. Each cluster of the plurality of clusters includes a plurality of HNA processing units (HPUs). A corresponding plurality of HPUs of a corresponding plurality of clusters of at least one selected super-cluster is available as a resource pool of HPUs to the HNA scheduler for assignment of at least one HNA instruction to enable acceleration of a match of at least one regular expression pattern in an input stream received from a network.

A wireless control device includes a power source, one or more sensors, one or more switches, a wireless transceiver circuit, an antenna connected to the wireless transceiver circuit, and a processor communicably coupled to the power source, the one or more sensors, the one or more switches, and the wireless transceiver circuit. The processor receives a data from the one or more sensors or the one or more switches, determines a pre-defined action associated with the data that identifies one or more external devices and one or more tasks, and transmits one or more control signals via the wireless transceiver circuit and the antenna that instruct the identified external device(s) to perform the identified task(s).

A wireless control device includes a power source, one or more sensors, one or more switches, a wireless transceiver circuit, an antenna connected to the wireless transceiver circuit, and a processor communicably coupled to the power source, the one or more sensors, the one or more switches, and the wireless transceiver circuit. The processor receives a data from the one or more sensors or the one or more switches, determines a pre-defined action associated with the data that identifies one or more external devices and one or more tasks, and transmits one or more control signals via the wireless transceiver circuit and the antenna that instruct the identified external device(s) to perform the identified task(s).

This information processing system inputs/outputs data normally, even when a serial communication bus is extended by network communication. The information processing system is provided with: a device; a device control unit for controlling the device; a device interface unit which interfaces with the device control unit; an information processing device provided with an application interface unit which interfaces with an application; a channel establishment unit which connects, via a communication unit, the application interface unit and the device interface unit, and establishes a control channel and a data channel between the application and the device; and an error suppression unit which suppresses the occurrence of error in data transfer over the channel established by the channel establishment unit.

The disclosure describes a display controller and a method that includes monitoring a fill-level of a first in, first out (FIFO) block in the display controller, generating a regulation signal that depends on the fill-level of the FIFO block, and regulating, based on the regulation signal, access to a system interconnect by a master unit other than the display controller.

A method includes transmitting, by a controller of a storage device, a first bit on a data line. The method further includes responsive to transmitting the first bit on the data line, determining, by the controller, a line level of the data line. The method further includes responsive to determining the line level of the data line, determining, by the controller, whether the line level of the data line corresponds to the first bit and responsive to determining that the line level of the data line does not correspond to the first bit, determining, by the controller, that a collision has occurred on the data line.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.

An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

A system, method and computer readable medium for operating a First In, First Out (FIFO) buffer that transfers data between a host and a plurality of endpoints using chip select is disclosed. The method includes receiving a current value of a read pointer and a status for an active endpoint and reading data at a location to which the read pointer points and setting a tag associated with the location to which the read pointer points to indicate availability.