A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, an adder tree, an accumulator, and a fixed-point to floating-point converter. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a single-precision floating-point (FP32) format to output multiplication result data of the FP 32 format. Each of the plurality of floating-point to fixed-point converters may convert the FP 32 format into a fixed-point format. The adder tree may perform a first addition operation on the data of the fixed-point format. The accumulator may perform an accumulation operation on the data output from the adder tree. And the fixed-point to floating-point converter may convert the data of the fixed-point format into data of the FP32 format.

A MAC operator includes a plurality of multipliers configured to perform a multiplication operation on a floating-point format first data and a floating-point format second data to output a floating-point format multiplication result data, a plurality of floating-point-to-fixed-point converters configured to receive the floating-point format multiplication result data from each of the plurality of multipliers and convert into a fixed-point format multiplication result data to be output, and an adder tree configured to perform an addition operation on the fixed-point format multiplication result data that is output from the plurality of floating-point-to-fixed-point converters. If a first mantissa of the first data and a second mantissa of the second data are composed of ‘M’-bit (‘M’ being a natural number), each of the plurality of multipliers is configured to perform the multiplication operation so that the fixed-point format multiplication result data includes a mantissa of 2*(M+1) bits.

Systems, apparatuses, and methods related to a neuron using posits are described. An example apparatus may include a memory array including a plurality of memory cells configured to store data. The data can include a plurality of bit strings. The example apparatus may include a neuron component coupled to the memory array. The neuron component can include neuron circuitry configured to perform neuromorphic operations on at least one of the plurality of bit strings.

An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

The present disclosure relates to a computing device for processing a multi-bit width value, an integrated circuit board card, a method, and a computer readable storage medium. The computing device may be included in a combined processing apparatus, and the combined processing apparatus may further include a general interconnection interface, and an other processing device. The computing device interacts with the other processing device to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage device connected to an apparatus and the other processing device and configured to store data of the apparatus and the other processing device. The solution of the present disclosure can split the multi-bit width value so that the processing capability of the processor is not influenced by the bit width.

A normalizer includes a “0” search circuit configured to search for a position of a most significant “0” bit of first mantissa data included in input data to output first search data, a “1” search circuit configured to search for a position of a most significant “1” bit of the first mantissa data included in the input data to output second search data, a selector configured to output one selected by a bit value of first sign data of the input data between the first search data and the second search data, as selected data, an exponent adder configured to add first exponent data included in the input data and the selected data to output second exponent data included in output data, and a mantissa shifter configured to perform a shifting operation on the first mantissa data, based on the selected data to output second mantissa data included in the output data.

A MAC operator includes a plurality of multipliers, a plurality of floating-point to fixed-point converters, and an adder tree. Each of the plurality of multipliers may perform a multiplication operation on first data and second data of a floating-point format to output multiplication result data. Each of the plurality of floating-point to fixed-point converters may convert the data type of the multiplication result data into a fixed-point format. The adder tree may perform a first addition operation on the multiplication result data of the fixed-point format. Each of the plurality of floating-point to fixed-point converters may skip a ‘+1’ operation for processing a negative number and a ‘+1’ operation for roundup processing in a data type converting process, and output round bits equaling to bit values not added by the skipped ‘+1’ operations in the data type converting process.

A neural network system includes a data type converter and a MAC operator. The data type converter may convert 32-bit floating-point format into one of a plurality of 16-bit floating-point formats. The MAC operator may perform MAC operations using 16-bit floating-point format data converted by the data type converter. The MAC operator includes a data type modulator configured to modulate the bit number of the converted 16-bit floating-point format to provide a modulated floating-point format with bit number different from the bit number of the converted 16-bit floating-point format.

An apparatus and method for efficiently performing a multiply add or multiply accumulate operation. For example, one embodiment of a processor comprises: a decoder to decode an instruction specifying an operation, the instruction comprising a first operand identifying a multiplier and a second operand identifying a multiplicand; and fused multiply-add (FMA) execution circuitry comprising first multiplication circuitry to perform a multiplication using the multiplicand and multiplier to generate a result for multipliers and multiplicands falling within a first precision range, and second multiplication circuitry to be used instead of the first multiplication circuitry for multipliers and multiplicands falling within a second precision range.

A processor comprising: a register file comprising a group of operand registers for holding data values, each operand register being a fixed number of bits in length for holding a respective data value of that length; and processing logic comprising floating point logic for performing floating point operations on data values in the register file, the floating point logic is configured to process the fixed number of bits in the respective data value according to a floating point format comprising a set of mantissa bits and a set of exponent bits. The processing logic is operable to select between a plurality of different variants of the floating point format, at least some of the variants having a different size sets of mantissa bits and exponent bits relative to one another.