A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

A Bias Unit Element (UE) has a digital input, a sign input, and a chop clock. The sign input is exclusive ORed with the chop clock to generate a signed chop clock. Each Bias UE comprises a positive Bias UE and a negative Bias UE, each comprising groups of NAND gates generating an output and a complementary output, each of which are coupled to differential charge transfer lines through binary weighted charge transfer capacitors to a differential charge transfer bus comprising a positive charge transfer line and a negative charge transfer line. The chopped sign input enables the positive Bias UE when the sign bit is positive and enables the negative Bias UE when the sign bit is negative.

A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

A planar fabrication charge transfer capacitor for coupling charge from a Unit Element (UE) generates a positive charge first output V_PP and a positive charge second output V_NP, the first output coupled to a positive charge line comprising a continuous first planar conductor, a continuous second planar conductor parallel to the first planar conductor, and a continuous third planar conductor parallel to the first planar conductor and second planar conductor, the charge transfer capacitor comprising, in sequence: a first co-planar conductor segment, the first planar conductor, a second co-planar conductor segment, the second planar conductor, a third co-planar conductor segment, the third planar conductor, and a fourth coplanar conductor segment, the first and third coplanar conductor segments capacitively edge coupled to the UE first output V_PP, the second and fourth coplanar conductor segments capacitively edge coupled to the UE second output V_NP.

Various embodiments of the invention allow to effectively reduce device and system power consumption in both active and inactive modes without compromising performance, without large area overhead, and at low cost. In certain embodiments, the reduction of power consumption is accomplished by combining circuit control techniques with power gating methods to reduce power loss due to leakage current.