Technologies are generally described for an array of logic elements effective to generate a data signal. A first logic element may include an input circuit, a comparator circuit, and a state machine. The input circuit may receive a first input state signal and a second input state signal from a second logic element and a third logic element, respectively. The input circuit may determine a sum based on the first and second input state signals. The comparator circuit may compare the sum with a threshold and, in response, may generate an intermediate signal based on the comparison. The state machine may identify a current state of the first logic element. The state machine may generate an output state signal based on the intermediate signal and the current state of the first logic element. The output state signal may indicate a subsequent state of the first logic element.

Technologies are generally described for an array of logic elements effective to generate a data signal. A first logic element may include an input circuit, a comparator circuit, and a state machine. The input circuit may receive a first input state signal and a second input state signal from a second logic element and a third logic element, respectively. The input circuit may determine a sum based on the first and second input state signals. The comparator circuit may compare the sum with a threshold and, in response, may generate an intermediate signal based on the comparison. The state machine may identify a current state of the first logic element. The state machine may generate an output state signal based on the intermediate signal and the current state of the first logic element. The output state signal may indicate a subsequent state of the first logic element.

Apparatuses and methods of manufacturing same, systems, and methods for performing recursive operations using a partial remainder-divisor (PD) table are described. In one aspect, it is determined whether a current cell in the PD table indicated by a current partial remainder/radicand row value and a current divisor/root column value is outside a primary region of the PD table. If the current cell is outside the primary region of the PD table, at least one of the current partial remainder/radicand row value and the current divisor/root column value are adjusted so that the indicated current cell falls within the primary region of the PD table.

Apparatuses and methods of manufacturing same, systems, and methods for generating a starting estimate for radix-16 square root iterative calculation using hardware, including a radix-4 partial remainder-divisor (PD) table, which is used for both division and square root operations, are described. In one aspect, a part of a radicand for a radix-16 square root iterative operation is used to determine column/root and row/partial radicand values, which are then used to determine a starting estimate from a radix-4 PD table for the radix-16 square root iterative operation.

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.

Apparatuses and methods of manufacturing same, systems, and methods for performing recursive operations using a partial remainder-divisor (PD) table are described. In one aspect, it is determined whether a current cell in the PD table indicated by a current partial remainder/radicand row value and a current divisor/root column value is outside a primary region of the PD table. If the current cell is outside the primary region of the PD table, at least one of the current partial remainder/radicand row value and the current divisor/root column value are adjusted so that the indicated current cell falls within the primary region of the PD table.

Apparatuses and methods of manufacturing same, systems, and methods for generating a starting estimate for radix-16 square root iterative calculation using hardware, including a radix-4 partial remainder-divisor (PD) table, which is used for both division and square root operations, are described. In one aspect, a part of a radicand for a radix-16 square root iterative operation is used to determine column/root and row/partial radicand values, which are then used to determine a starting estimate from a radix-4 PD table for the radix-16 square root iterative operation.

An integrated circuit may include a floating-point adder that supports variable precisions. The floating-point adder may receive first and second inputs to be added, where the first and second inputs each have a mantissa and an exponent. The mantissa and exponent values may be split into a near path and a far path using a dual path floating-point adder architecture depending on the difference of the exponents and on whether an addition or subtraction is being performed. The mantissa values may be left justified, while the sticky bits are right justified. The hardware for the largest mantissa can be used to support the calculations for the smaller mantissas using no additional arithmetic structures, with only some multiplexing and decoding logic.

System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.

A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.