An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions. The method also includes repeating the ripple selecting group carry-out values, until all group carry out values have been selected.

A method comprises receiving a first N-bit unsigned number and a second N-bit unsigned number, receiving a control signal indicating a m-bit shifting operation and processing the first N-bit unsigned number, the second N-bit unsigned number and the control signal in an add-and-shift apparatus, wherein an addition/subtraction operation and the m-bit shifting operation are performed in parallel in the add-and-shift apparatus.

The present disclosure relates generally to techniques for enhancing adders implemented on an integrated circuit. In particular, arithmetic performed by an adder implemented to receive operands having a first precision is restructured so that a set of sub-adders performs the arithmetic on a respective segment of the operands. More specifically, the adder is restructured, and a decoder determines a generate signal and a propagate signal for each of the sub-adders and routes the generate signal and the propagate signal to a prefix network. The prefix network determines respective carry bit(s), which carries into and/or select a sum at a subsequent sub-adder.

A method for an associative memory device includes performing in parallel multi-bit operations of P pairs of multi-bit operands stored in columns of a memory array, each pair is stored in a different column, each bit i of each multi-bit operands of each pair is stored in a row of a section i in the column and each operation occurs in its associated column. A system includes a non-destructive associative memory array with multiple sections, each section j includes cells arranged in rows and columns, to store a bit j from a first multi-bit number in a first row and a bit j from a second multi-bit number in a second row of a same column, and a concurrent adder to, in parallel, perform per-section operations in each section, that includes one or more Boolean operations between a plurality of bits stored in rows of the section.

An adder includes a primary carry bit generation circuit and a summing circuit. The primary carry bit generation circuit is configured to generate first carry bits for a first number of pairs of bits from first and second operands, and to generate second carry bits for a second number of pairs of bits from the first and second operands. The second number of pairs being different than the first number of pairs. The summing circuit is configured to generate first sums by adding bits of pairs from the first and second number of pairs and the first and second carry bits. The summing circuit is configured to generate second sums by adding bits of other pairs of the bits from first and second operands than the pairs in the first and second number of pairs and additional carry bits generated when adding the bits of the other pairs.

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.

A method for an associative memory device includes storing a plurality of pairs of N-bit numbers A and B to be added together in columns of a memory array of the associative memory device, each pair in a column, each bit in a row of the column, and dividing each N-bit number A and B into groups containing M bits each, having group carry-out predictions for every group except a first group, the group carry-out predictions calculated for any possible group carry-in value, and, once the carry-out value for a first group is calculated, selecting the next group carry out value from the group carry-out predictions. The method also includes repeating the ripple selecting group carry-out values, until all group carry out values have been selected.

A logic cell for a programmable logic integrated circuit having K function inputs, where K is the largest number such that the logic cell can compute any function of K inputs, and where the logic cell is configurable to implement one bit of a counter in parallel with any independent function of K-1 of the K inputs.

An integrated circuit that includes very large adder circuitry is provided. The very large adder circuitry receives more than two inputs each of which has hundreds or thousands of bits. The very large adder circuitry includes multiple adder nodes arranged in a tree-like network. The adder nodes divide the input operands into segments, computes the sum for each segment, and computes the carry for each segment independently from the segment sums. The carries at each level in the tree are accumulated using population counters. After the last node in the tree, the segment sums can then be combined with the carries to determine the final sum output. An adder tree network implemented in this way asymptotically approaches the area and performance latency as an adder network that uses infinite speed ripple carry adders.