An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Systems, apparatuses, and methods for implementing a fractional pointer lookup table are disclosed. A system includes a fractional pointer lookup table and control logic coupled to the table. The control logic performs an access to the table with a numerator and a denominator, wherein the numerator and the denominator are integers. The control logic receives a result of the lookup, wherein the result is either a rounded-up value of a quotient of the numerator and denominator or a rounded-down value of the quotient. In one embodiment, the control logic provides a fractional pointer to the table with each access and receives a fractional pointer limit from the table. The control logic initializes the fractional pointer to zero, increments the fractional pointer after each access to the table, and resets the fractional pointer to zero when the fractional pointer reaches the fractional pointer limit.

A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

Computing a non-linear function (x) in hardware or embedded systems can be complex and resource intensive. In one or more aspects of the disclosure, a method, a computer-readable medium, and an apparatus are provided for computing a non-linear function (x) accurately and efficiently in hardware using look-up tables (LUTs) and interpolation or extrapolation. The apparatus may be a processor. The processor computes a non-linear function (x) for an input variable x, where (x)=g(y(x),z(x)). The processor determines an integer n by determining a position of a most significant bit (MSB) of an input variable x. In addition, the processor determines a value for y(x) based on a first look-up table and the determined integer n. Also, the processor determines a value for z(x) based on n and the input variable x, and based on a second look-up table. Further, the processor computes (x) based on the determined values for y(x) and z(x).

A binary logic circuit for determining the ratio x/d in accordance with a rounding scheme, where x is a variable integer input of bit length w and d is a fixed positive integer of the form 2.sup.n1, the binary logic circuit being configured to form the ratio as a plurality of bit slices, the bit slices collectively representing the ratio, wherein the binary logic circuit is configured to generate each bit slice according to a first modulo operation for calculating mod(2.sup.n1) of a respective bit selection of the input x and in dependence on a check for a carry bit, wherein the binary logic circuit is configured to, responsive to the check, selectively combine a carry bit with the result of the first modulo operation.

An integrated circuit device includes multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values. Each column of the plurality of columns includes one or more subproducts of a plurality of subproducts. The integrated circuit device also includes adder circuitry configured to determine a plurality of sums, each sum being a sum of one column of the plurality of columns. A first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value and second value that are associated with the first column and a third value associated with a second column of the plurality of columns that differs from the first column. The third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns.

A method includes retrieving, at a processor, a first instruction for performing a first piecewise Horner's method operation for a polynomial and executing the first instruction. Executing the first instruction causes the processor to perform operations including accessing one or more look-up tables based on an interval of a first function input to determine a first coefficient of the polynomial for the first input range. The operations also include determining a first partial polynomial output of the first piecewise Horner's method operation. Determining the first partial polynomial output includes multiplying a first partial polynomial input with the first function input to generate a first partial value and adding the first coefficient to the first partial value to determine the first partial polynomial output.

An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Computing a non-linear function (x) in hardware or embedded systems can be complex and resource intensive. In one or more aspects of the disclosure, a method, a computer-readable medium, and an apparatus are provided for computing a non-linear function (x) accurately and efficiently in hardware using look-up tables (LUTs) and interpolation or extrapolation. The apparatus may be a processor. The processor computes a non-linear function (x) for an input variable x, where (x)=g(y(x),z(x)). The processor determines an integer n by determining a position of a most significant bit (MSB) of an input variable x. In addition, the processor determines a value for y(x) based on a first look-up table and the determined integer n. Also, the processor determines a value for z(x) based on n and the input variable x, and based on a second look-up table. Further, the processor computes (x) based on the determined values for y(x) and z(x).