A data processing apparatus to perform a digit-recurrence operation on an input value comprises receiver circuitry for receiving a remainder value of a previous iteration of the digit-recurrence operation. Comparison circuitry performs comparisons on most significant bits of the remainder value of the previous iteration of the digit-recurrence operation with each of a plurality of selection constants associated with available digits of a next digit of a result of the digit-recurrence operation and outputs the next digit of the result of the digit-recurrence operation based on the comparisons. Each of the selection constants is associated with one of the available digits and an input parameter. Storage circuitry stores a subset of the selection constants, the subset of the selection constants excluding an excluded selection constant from the selection constants, which is associated with an excluded digit from the available digits.

A method and apparatus for processing numeric calculation are provided. The method includes determining a shift bit and an index bit that falls within an index range of a lookup table from among bits representing a divisor scaled up by an offset, obtaining a replacement value corresponding to an index value of the determined index bit by using the lookup table, multiplying a dividend scaled up by the offset by the obtained replacement value, and outputting a value corresponding to a division operation by correcting a scale of a result of the multiplication using a right shift operation.

A computation unit computes a function f(I). The function f(I) has a target output range over a first domain of an input I encoded using a first format. A first circuit receives the encoded input I in the first format including X bits, to add an offset C to the encoded input I to generate an offset input SI=I+C, in a second format including fewer than X bits. The offset C is equal to a difference between the first domain in f(I) and a higher precision domain of the second format for the offset input SI. A second circuit is operatively coupled to receive the offset input SI in the second format, to output a value equal to a function f(SI) to provide an encoded output value f(I).

Methods and systems for performing hardware computations of mathematical functions are provided. In one example, a system comprises a mapping table that maps each base value of a plurality of base values to parameters related to a mathematical function; a selection module configured to select, based on an input value, a first base value and first parameters mapped to the first base value in the mapping table; and arithmetic circuits configured to: receive, from the mapping table, the first base value and the first plurality of parameters; and compute, based on a relationship between the input value and the first base value, and based on the first parameters, an estimated output value of the mathematical function for the input value.

A computation unit computes a function f(I). The function f(I) has a target output range over a first domain of an input I encoded using a first format. A first circuit receives the encoded input I in the first format including X bits, to add an offset C to the encoded input I to generate an offset input SI=I+C, in a second format including fewer than X bits. The offset C is equal to a difference between the first domain in f(I) and a higher precision domain of the second format for the offset input SI. A second circuit is operatively coupled to receive the offset input SI in the second format, to output a value equal to a function f(SI) to provide an encoded output value f(I).

A processor-implemented data processing method includes: normalizing input data of an activation function comprising a division operation; determining dividend data corresponding to a dividend of the division operation by reading, from a memory, a value of a first lookup table addressed by the normalized input data; determining divisor data corresponding to a divisor of the division operation by accumulating the dividend data; and determining output data of the activation function corresponding to an output of the division operation obtained by reading, from the memory, a value of a second lookup table addressed by the dividend data and the divisor data.

Methods and systems for performing hardware computations of mathematical functions are provided. In one example, a system comprises a mapping table that maps each base value of a plurality of base values to parameters related to a mathematical function; a selection module configured to select, based on an input value, a first base value and first parameters mapped to the first base value in the mapping table; and arithmetic circuits configured to: receive, from the mapping table, the first base value and the first plurality of parameters; and compute, based on a relationship between the input value and the first base value, and based on the first parameters, an estimated output value of the mathematical function for the input value.

Control circuitry coupled to a multiply unit which includes a plurality of stage, each of which may be configured to perform a corresponding arithmetic function, may be configured to retrieve a given entry from a lookup table dependent upon a first portion of a binary representation of an input operand. An error value of an error function evaluated dependent upon a lookup value in a given entry of the plurality of entries is included in a predetermined error range. The control circuitry may be further configured to determine an initial approximation of a result of an iterative arithmetic operation using the first entry and initiate the iterative arithmetic operation using the initial approximation and the input operand.

Systems and methods are disclosed for minimizing reads for reallocated sectors of a data storage medium. An apparatus may be configured to selectively skip over reallocated sectors in an LBA range without interrupting a read, via generating a skip mask or by beginning the read after the reallocated sector and reading the entire track up to the reallocated sector. When a number of sectors not read from the LBA range during the read operation is less than an amount of sectors that can be recovered based on an error correction capability, the data of the reallocated sector may be reconstructed using error correction data rather than by performing a read at the reallocated sector.

Systems, apparatuses, and methods for implementing a fractional pointer lookup table are disclosed. A system includes a fractional pointer lookup table and control logic coupled to the table. The control logic performs an access to the table with a numerator and a denominator, wherein the numerator and the denominator are integers. The control logic receives a result of the lookup, wherein the result is either a rounded-up value of a quotient of the numerator and denominator or a rounded-down value of the quotient. In one embodiment, the control logic provides a fractional pointer to the table with each access and receives a fractional pointer limit from the table. The control logic initializes the fractional pointer to zero, increments the fractional pointer after each access to the table, and resets the fractional pointer to zero when the fractional pointer reaches the fractional pointer limit.