An arithmetic processing method is provided using a binary fixed-point arithmetic processing circuit to carry out an operation of multiplicatively dividing a dividend by a divisor. The method comprises shifting the divisor by a specific number of bits when the absolute value of the divisor is within a specific range, and holding the divisor without shifting the divisor when the absolute value of the divisor is out of the specific range, acquiring an initial value of approximation calculation for the divisor that is shifted or held without being shifted, calculating a reciprocal of the divisor by performing asymptotic approximation of the acquired initial value more than once, and calculating a product of the calculated reciprocal and the dividend, and shifting the calculated product by the specific number of bits when the divisor is shifted.

Provided is a fast divider including an initial parameter setting unit and an arithmetic unit. The arithmetic unit is coupled to the initial parameter setting unit that receives a divisor and a dividend, and sets a plurality of initial parameters of a sequence according to the divisor and the dividend. The plurality of initial parameters includes an initial term, a first term and a common ratio having an absolute value smaller than 1. The arithmetic unit stores a recurrence relation of the sequence and iteratively computes a quotient using the recurrence relation according to the plurality of initial parameters. The recurrence relation indicates that a (k+1).sup.th term is equal to a product of a k.sup.th term multiplied by a sum of the common ratio and 1 subtracted by a product of a (k−1).sup.th term multiplied by the common ratio. k is an integer larger than or equal to 1.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

Various embodiments are provided for conducting a power flow analysis using a set of line-wise power balance equations. In at least some embodiment, the set of line-wise power balance equations is solved using a Newton-Raphson technique. In various cases, the Jacobian matrix generated by the Newton-Raphson technique may directly indicate the transmission lines, or sets of transmission lines, which are most susceptible to voltage collapse. In at least one example application, the set of line-wise power balance equations may be used as equality constraints in an optimal power flow (OPF) formulation for solving an optimal power flow (OPF) problem.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

An execution unit for a processor, the execution unit comprising: a look up table; a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry comprising a natural logarithm associated with the index value; control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate terms of a Taylor series expansion of a natural logarithm, wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of a natural logarithm of the operand.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

An execution unit for a processor, the execution unit comprising: a look up table having a plurality of entries, each of the plurality of entries comprising an initial estimate for a result of an operation; a preparatory circuit configured to search the look up table using an index value dependent upon the operand to locate an entry comprising a first initial estimate for a result of the operation; a plurality of processing circuits comprising at least one multiplier circuit; and control circuitry configured to provide the first initial estimate to the at least one multiplier circuit of the plurality of processing circuits so as perform processing, by the plurality of processing units, of the first initial estimate to generate the function result, said processing comprising applying one or more Newton Raphson iterations to the first initial estimate.

An execution unit for a processor, the execution unit comprising: a look up table; a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry comprising a natural logarithm associated with the index value; control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate terms of a Taylor series expansion of a natural logarithm, wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of a natural logarithm of the operand.

Various embodiments are provided for conducting a power flow analysis using a set of line-wise power balance equations. In at least some embodiment, the set of line-wise power balance equations is solved using a Newton-Raphson technique. In various cases, the Jacobian matrix generated by the Newton-Raphson technique may directly indicate the transmission lines, or sets of transmission lines, which are most susceptible to voltage collapse. In at least one example application, the set of line-wise power balance equations may be used as equality constraints in an optimal power flow (OPF) formulation for solving an optimal power flow (OPF) problem.