Hardware logic arranged to perform modulo calculation with respect to a constant value b is described. The modulo calculation is based on a finite polynomial ring with polynomial coefficients in GF(2). This ring is generated using a generator polynomial which has a repeat period (or cycle length) which is a multiple of b. The hardware logic comprises an encoding block which maps an input number into a plurality of encoded values within the ring and a decoding block which maps an output number back from the ring into binary. A multiplication block which comprises a tree of multipliers (e.g. a binary tree) takes the encoded values and multiplies groups (e.g. pairs) of them together within the ring to generate intermediate values. Groups (e.g. pairs) of these intermediate values are then iteratively multiplied together within the ring until there is only one intermediate value generated which is the output number.

Embodiments of the invention include an apparatus for performing Galois multiplication using an enhanced Galois table. Galois multiplication may include converting a first and second multiplicand to exponential forms using a Galois table, adding the exponential forms of the first and second multiplicands, and converting the added exponential forms of the first and second multiplicands to a decimal equivalent binary form using the Galois table to decimal equivalent binary result of the Galois multiplication.