The method comprises: connecting to a plurality of AI computing boards in an AI processing resource pool and a plurality of video encoding and decoding boards in a video processing resource pool by means of a unified high-speed interface; respectively allocating a specified number of AI computing boards and video encoding and decoding boards on account of resources and bandwidths required for completing a processing task to form a temporary cooperation relationship based on the processing task; in response to resource overflow or insufficiency in the AI processing resource pool or the video processing resource pool caused by a processing task change, accessing more AI computing boards or video encoding and decoding boards or stopping using redundant AI computing boards or video encoding and decoding boards; performing the processing task on account of the allocated AI computing boards or video encoding and decoding boards, and releasing the temporary cooperation relationship.

A real-time computational device includes a programmable real-time processor, a communications input port which is connected to the programmable real-time processor through a first broadside interface, and a communications output port which is connected to the programmable real-time processor through a second broadside interface. Both broadside interfaces enable 1024 bits of data to be transferred across each of the broadside interfaces in a single clock cycle of the programmable real-time processor.

Techniques described herein relate to a method for performing computational offloads for composed information handling systems. The method includes obtaining, by a system control processor associated with a composed information handling system, a computational offload request associated with a dataset from an application executing on an at least one compute resource set; in response to obtaining the computational offload request: identifying a dataset location associated with the dataset in the composed information handling system; identifying resources of the composed information handling system capable of performing the computational offload request; selecting a resource of the resources to perform the computational offload; and initiating performance of the computational offload request on the selected resource.

A method, computer program product, and computing system for allocating a first set of cores of a plurality of cores of a multicore central processing unit (CPU) for processing host input-output (IO) operations of a plurality of operations on a storage system. A second set of cores of the plurality of cores may be allocated for processing flush operations of the plurality of operations on the storage system. A third set of cores of the plurality of cores may be allocated for processing rebuild operations of the plurality of operations on the storage system. At least one of one or more host IO operations, one or more rebuild operations, and one or more flush operations may be processed, via the plurality of cores and based upon, at least in part, the allocation of the plurality of cores for processing the plurality of operations.

Systems and methods are provided for offloading a task from a central processor in a radio access network (RAN) server to one or more heterogeneous accelerators. For example, a task associated with one or more operational partitions (or a service application) associated with processing data traffic in the RAN is dynamically allocated for offloading from the central processor based on workload status information. One or more accelerators are dynamically allocated for executing the task, where the accelerators may be heterogeneous and may not comprise pre-programming for executing the task. The disclosed technology further enables generating specific application programs for execution on the respective heterogeneous accelerators based on a single set of program instructions. The methods automatically generate the specific application programs by identifying common functional blocks for processing data traffic and mapping the functional blocks to the single set of program instructions to generate code native to the respective accelerators.

A first deep learning accelerator (DLA) model can be executed using a first subset of a plurality of DLA cores of a DLA chip. A second DLA model can be executed using a second subset of the plurality of DLA cores of the DLA chip. The first subset can include a first quantity of the plurality of DLA cores. The second subset can include a second quantity of the plurality of DLA cores that is different than the first quantity of the plurality of DLA cores.

Virtualization techniques can include determining virtual function routing tables for the virtual parallel processing units (PPUs) from a logical topology of a virtual function. A first mapping of the virtual PPUs to a first set of a plurality of physical PPUs can be generated. Virtualization can also include generating a first set of physical function routing tables for the first set of physical PPUs based on the virtual function tables and the first virtual PPU to physical PPU mapping. An application can be migrated from the first set of physical PPUs to a second set of PPUs by generating a second mapping of the virtual PPUs to a second set of a plurality of physical PPUs. A second set of physical function routing table for the second set of physical PPUs can also be generated based on the virtual function tables and the second virtual PPU to physical PPU mapping.

A method for managing client resources by receiving a desired load factor representing the number of instructions being executed per second (IOPS) to implement an application on a set of cores of a client device, based on the desired load factor and a latency factor, determining a maximum number of IOPS that can be executed by the cores of the client device before reaching system saturation, determining a pattern of the IOPS being executed on the set of cores based on historical IOPS information for the latency factor, and based on the historical IOPS information, determining to execute the IOPS on a subset of the set of cores.

A method is provided for configuring an SIL simulation of a control unit running on a computer, software modules for the control unit, which have a plurality of tasks, being installed on the computer for the SIL simulation of the control unit, the tasks being processed in a predetermined clock cycle having a periodic period between the individual clock time points, and the computer including a plurality of processor cores, on which a plurality of virtual machines run, which each process predetermined tasks. A possibility is thus provided for minimizing the computing time of an SIL test.

A technique for job distribution within a grid environment includes receiving jobs at a submission cluster for distribution of the jobs to at least one of a plurality of execution clusters where each execution cluster includes one or more execution hosts. Resource attributes are determined corresponding to each execution host of the execution clusters. Resource requirements are determined for the job and candidate execution clusters are identified for processing the job based on the resource attributes of the execution hosts and the resource requirements of the job. An optimum execution cluster is selected from the candidate execution clusters for allocating the job thereto for execution of the job based on a weighting factor applied to select resources of the respective execution clusters.