An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Disclosed herein is an enhanced volume manager (VM) for a storage system that accelerates input/output (I/O) performance for random write operations to a striped disk array using parity. More specifically, various implementations are directed to accelerating random writes (writes comprising less than a complete stripe of data) by consolidating several random writes together to create a sequential write (a full-stripe write) to eliminate one or more read operations and/or increase the volume of new/updated data stored for each write operation. Several such implementations comprise functionality in the VM (volume manager) for identifying random write I/O requests, queuing them locally in a journal, and then periodically flushing the journal to the disk array as a sequential write request.

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.