An emulation mitigation module is configured to mitigate emulation of legacy write requests on advanced disk devices using cached data stored in a cache memory of a storage system. A legacy write request may comprise write data blocks formatted in a legacy sector size while an advanced disk device may be formatted in an advanced sector size. The emulation mitigation module may execute a first method for modifying write requests using cached data, a second method for enforcing a minimum requested data size sent to the advanced disk device, and/or a third method for conditionally retrieving data from the advanced disk device and storing to cache. In some embodiments, the second and/or third method may be used with the first method to increase the effectiveness of the first method. The emulation mitigation module may improve performance and/or data integrity for of processing legacy write requests.

A method of merging data frames includes: receiving a first data frame having a plurality of sectors; receiving a second data frame having a plurality of sectors; generating a merged output data frame by merging, using a plurality of data paths including a plurality of multiplexers, sectors of the second data frame with sectors of the first data frame; and performing an error check on at least one check-data frame having sectors corresponding to those in the first data frame or the second data frame, where at least some of the sectors in the check-data frame are transmitted on a subset of the plurality of data paths that transmits sectors of the merged output data frame, and where the error check verifies the merged output data frame.

Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.

Embodiments herein provide for avoiding address collisions in a memory device. In one embodiment, a memory controller includes a command scheduler operable to process a read-modify-write I/O command to a location in memory, to detect another I/O command to the same memory location while the read-modify-write I/O command is accessing the memory location, and to stall the other I/O command until the read-modify-write I/O command is complete while allowing a third I/O command to access the memory.