G06F2211/1097

COMMAND SCHEDULER FOR A DISPLAY DEVICE
20170262958 · 2017-09-14 ·

Systems and methods consistent with the present disclosure may be utilized to negate the distinction between a display device operating in video and command modes in that commands associated with either mode are prioritized and executed according to a command scheduler consistent with the present disclosure. A command scheduler consistent with the present disclosure includes a display driver stack and a scheduler coupled to the display driver stack. The scheduler is configured to receive commands from the driver stack. Further, the scheduler is configured to queue and schedule the commands to be executed during a boot environment and during runtime. A host controller may also be coupled to the scheduler and may receive at least one of the commands from the scheduler. In time, the host controller transfers the commands to a device for execution.

Bidirectional trust chaining for trusted boot

A root of trust may include one or more hardware components of an IHS (Information Handling System) that operate using validated hardware instructions. Once a root of trust has been established, it may be extended by validating additional components and the instructions by which these components operate. A chain of trusted boot components may be used to securely initialize a set of components required to support core functions of the IHS. In order to detect components of a trusted boot chain that have been compromised, boot chain components validate their own instructions as well as the instructions to be utilized by the next boot component and the instructions utilized by the prior boot component, thus providing bidirectional validation of trusted boot chain components.

Cable unit for connecting devices to enable wireless exchange of data and/or power between them

The present invention relates to a cable unit for connecting devices in a system, in particular in a patient monitoring system, to enable wireless exchange of data and/or power between them. The proposed cable unit comprises a cable (510) and a connector (520, 530) arranged at each end of said cable, said connector comprising a data transmission unit (522, 532) for transmitting data to and/or receiving data from a device having a counterpart connector and a magnetic coupling unit (521, 531) for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling.

Chassis internal device security

Methods, systems, and computer programs encoded on computer storage medium, for verifying, by a mask ROM of a CPU of a first computing device and with fused keys included by the CPU, a boot loader that is included by a flash memory of the first computing device, in response to verifying the boot loader, verifying, by the boot loader and with boot loader keys included by the flash memory, a kernel included by the a memory device of the first computing device, in response to verifying the kernel, decrypting, by the kernel using a hidden root key (HRK) included by the CPU of the first computing device, a device unique certification (DUC) included by the flash memory, in response to decrypting the DUC, generating, by the first computing device, a proof-of-possession of the DUC.

Vehicle

A vehicle includes a first display circuit and a second display circuit. The first display circuit is disposed at a position capable of being visually checked by a driver. The second display circuit is disposed at a position capable of being visually checked by a driver. The first display circuit can display at least information about autonomous driving. The second display circuit can display at least information other than the information about the autonomous driving. First display circuit has first redundancy. The second display circuit has second redundancy lower than the first redundancy.

BIDIRECTIONAL TRUST CHAINING FOR TRUSTED BOOT
20210019419 · 2021-01-21 · ·

A root of trust may include one or more hardware components of an IHS (Information Handling System) that operate using validated hardware instructions. Once a root of trust has been established, it may be extended by validating additional components and the instructions by which these components operate. A chain of trusted boot components may be used to securely initialize a set of components required to support core functions of the IHS. In order to detect components of a trusted boot chain that have been compromised, boot chain components validate their own instructions as well as the instructions to be utilized by the next boot component and the instructions utilized by the prior boot component, thus providing bidirectional validation of trusted boot chain components.

Fault tolerant and diagnostic boot
10838815 · 2020-11-17 · ·

A method for processing data is provided that includes starting a processor from an off state and loading watchdog timer handler code into a processor memory. Executing the watchdog timer handler code and determining whether a catastrophic error has occurred during execution of the watchdog timer handler code. Invoking a system management module to update error code if it is determined that the catastrophic error has occurred and invoking a first phase dispatcher to set up a first stack frame associated with a first phase if it is determined that a catastrophic error has not occurred.

CHASSIS INTERNAL DEVICE SECURITY

Methods, systems, and computer programs encoded on computer storage medium, for verifying, by a mask ROM of a CPU of a first computing device and with fused keys included by the CPU, a boot loader that is included by a flash memory of the first computing device, in response to verifying the boot loader, verifying, by the boot loader and with boot loader keys included by the flash memory, a kernel included by the a memory device of the first computing device, in response to verifying the kernel, decrypting, by the kernel using a hidden root key (HRK) included by the CPU of the first computing device, a device unique certification (DUC) included by the flash memory, in response to decrypting the DUC, generating, by the first computing device, a proof-of-possession of the DUC.

FAULT TOLERANT AND DIAGNOSTIC BOOT
20200089571 · 2020-03-19 · ·

A method for processing data is provided that includes starting a processor from an off state and loading watchdog timer handler code into a processor memory. Executing the watchdog timer handler code and determining whether a catastrophic error has occurred during execution of the watchdog timer handler code. Invoking a system management module to update error code if it is determined that the catastrophic error has occurred and invoking a first phase dispatcher to set up a first stack frame associated with a first phase if it is determined that a catastrophic error has not occurred.

Integrated circuit device and system on a chip (SOC) for reducing boot time

A system on a chip (SOC) and an integrated circuit device having the same are disclosed. The SOC has a chip controller and a first chip element which do not need to operate according to a reference clock signal, and the SOC has a second chip element which needs to operate according to the reference clock signal. During resetting of a main system processor, the chip controller of the SOC is reset simultaneously. After the chip controller finishes resetting, the first chip element is then reset. After the main system processor finishes resetting, the second chip element of the SOC starts to reset. Accordingly, during the resetting of the main system processor, the SOC is reset simultaneously, thereby reducing the boot time of the integrated circuit device.