An apparatus includes a processor and split-read control circuitry (SRCC). The processor is to issue a set of one or more split-read requests for loading one or more data values to one or more respective local registers of the processor. The SRCC is to receive the set of one or more split-read requests, to read the one or more data values on behalf of the processor, and to write the data values into the one or more respective local registers. The processor and the SRCC are to coordinate a status of the split-read requests via a split-read-status indication.

A memory safety interface module (MSIM) configured to test a memory. The MSIM receives an original data from a digital logic and inverts the bits of the original data to generate an inverted data. It writes the inverted data to the memory address. The MSIM reads the inverted data from the memory address and determines whether the memory address and the inverted data are correct. The MSIM either writes the original data to the memory address in response to the memory address and the inverted data being correct or transmits an error indication in response to at least one of the memory address and the inverted data being incorrect. The MSIM reads the original data from the memory address and determines whether the memory address and the original data are correct or transmits an error indication in response to at least one of the memory address and the original data being incorrect.

Methods for controlled segregation of blocks of information encoded in the sequence of a biopolymer, such as nucleic acids and polypeptides, with rapid retrieval based on multiply addressing nanostructured data have been developed. In some embodiments, sequence controlled polymer memory objects include data-encoded biopolymers of any length or form encapsulated by natural or synthetic polymers and including one or more address tags. The sequence address labels are used to associate or select memory objects for sequencing read-out, enabling organization and access of distinct memory objects or subsets of memory objects using Boolean logic. In some embodiments, a memory object is a single-stranded nucleic acid scaffold strand encoding bit stream information that is folded into a nucleic acid nanostructure of arbitrary geometry, including one or more sequence address labels. Methods for controlled degradation of biopolymer-encoded blocks of information in the memory objects are also developed.

one embodiment of a memory stores information, including address bits, on DNA strands and provides access using a pipeline of tubes, where each tube selectively transfers half of the strands to the next tube based on probing of associated address bits. Transfers are controlled by logic relating to the state of the tubes: The pipeline may be initialized to start at a high-order target address, providing random access without enzymes, synthesizing probe molecules or PCR at access time. Thereafter, a processing unit gets fast access to sequentially addressed strands each cycle, for applications like executing machine language instructions or reading blocks of data from a file. Another embodiment with a compare unit allows low-order random access. Provided that addresses are encoded using single-stranded regions of DNA where probe molecules may hybridize, other information may use any DNA encoding. Electronic/electrochemical (electrowetting, nanopore, etc.) embodiments as well as biochemical embodiments are possible.

According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.

A memory controller configured to control a dynamic random access memory (DRAM) includes a first control circuit and a second control circuit. The first control circuit is configured to store a request received by the memory controller in a first storage circuit, and select a request from all requests stored in the first storage circuit. The second control circuit is configured to store the request selected by the first control circuit in a second storage circuit, reorder requests stored in the second storage circuit, generate a DRAM command, and issue the DRAM command to the DRAM. The first control circuit is configured to select the request based on target banks and target pages of the requests stored in the second storage circuit, and a state of a bank or page of the DRAM.

Provided are a computer program product, integrated cache manager, and method for maintaining data in a first level memory and buckets representing regions of memory devices to extend data cache. A plurality of buckets represent distinct regions of memory devices. The buckets are associated with different threshold access count ranges. Data having an access count is stored in one of the buckets associated with a threshold access count range including the access count of the data to store. Data evicted from a first level memory is copied to an initial bucket comprising one of the buckets. Data is moved from a source bucket comprising one of the buckets, including the initial bucket, to a target bucket of the buckets having a target threshold access count range including an access count of the data to move.

A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

The present disclosure provides a memory management method, and belongs to the technical field of networks. The method includes: allocating a first memory address to video frame data based on a memory multiplexing queue, wherein the memory multiplexing queue records a memory address of video frame data that has been rendered; storing the video frame data in a memory space indicated by the first memory address; and adding the first memory address to the memory multiplexing queue after performing rendering based on the video frame data.

Throughput is preserved in a distributed system while maintaining concurrency by pushing a commit wait period to client commit paths and to future readers. As opposed to servers performing commit waits, the servers assign timestamps, which are used to ensure that causality is preserved. When a server executes a transaction that writes data to a distributed database, the server acquires a user-level lock, and assigns the transaction a timestamp equal to a current time plus an interval corresponding to bounds of uncertainty of clocks in the distributed system. After assigning the timestamp, the server releases the user-level lock. Any client devices, before performing a read of the written data, must wait until the assigned timestamp is in the past.