A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having with a cache and connected to a corresponding memory, a computing device accessing one of the memories, includes monitoring memory access to any of the memories; monitoring cache coherency commands between computing devices; and identifying the computing device accessing one of the memories by using information related to the memory access and cache coherency commands.

A router device may receive a copy of a file. The router device may identify metadata associated with the copy of the file. The router device may process the metadata to identify a priority position in a first data structure associated with the router device. The router device may cause a copy of the file to be stored as a cached version of the file at the priority position in the first data structure. The router device may generate a copy of the cached version of the file. The router device may send the copy of the cached version of the file to a user device.

A router device may receive, from a user device, a request for access to a file. The router device may determine that a cached version of the file is stored in a first data structure associated with the router device. The router device may communicate with a server device to determine whether the cached version of the file is current. The server device may be associated with a second data structure that stores a master version of the file. The router device may generate a copy of the cached version of the file based on communicating with the server device. The router device may send the copy of the cached version of the file to the user device.

A router device may receive a copy of a file. The router device may identify metadata associated with the copy of the file. The router device may process the metadata to identify a priority position in a first data structure associated with the router device. The router device may cause a copy of the file to be stored as a cached version of the file at the priority position in the first data structure. The router device may generate a copy of the cached version of the file. The router device may send the copy of the cached version of the file to a user device.

A cache system may maintain size and/or request rate metrics for objects in a lower level cache and for objects in a higher level cache. When an L1 cache does not have an object, it requests the object from an L2 cache and sends to the L2 cache aggregate size and request rate metrics for objects in the L1 cache. The L2 cache may obtain a size metric and a request rate metric for the requested object and then determine, based on the aggregate size and request rate metrics for the objects in the L1 cache and the size metric and the request rate metric for the requested object in the L2 cache, an indication of whether or not the L1 cache should cache the requested object. The L2 cache provides the object and the indication to the L1 cache.

A computational system includes one or more processors. Each processor has multiple registers, as well attached memory to hold instructions. The processor is coupled to one or more broadside interfaces. A broadside interface allows the processor to load or store an entire widget state in a single clock cycle of the processor. The broadside interface also allows the processor to move and store 32 bytes of information into RAM in less than four to five clock cycles of the processor while the processor concurrently performs one or more mathematical operations on the information while the move and store operation is taking place.

A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.

Techniques for offload device address translation fetching are disclosed. In the illustrative embodiment, a processor of a compute device sends a translation fetch descriptor to an offload device before sending a corresponding work descriptor to the offload device. The offload device can request translations for virtual memory address and cache the corresponding physical addresses for later use. While the offload device is fetching virtual address translations, the compute device can perform other tasks before sending the corresponding work descriptor, including operations that modify the contents of the memory addresses whose translation are being cached. Even if the offload device does not cache the translations, the fetching can warm up the cache in a translation lookaside buffer. Such an approach can reduce the latency overhead that the offload device may otherwise incur in sending memory address translation requests that would be required to execute the work descriptor.

A bridge apparatus includes slave circuits connected to each other via a bus. Each of the slave circuits is connected to one of master apparatuses, function as a slave for the master apparatus connected thereto, and performs communication in accordance with a protocol in which the number of masters in a system is restricted. Addresses of memories are respectively set in the slave circuits, and the memories are connected to the master apparatuses to which the slave circuits are respectively connected. When a first master apparatus accesses a memory connected to a second master apparatus by specifying a first address of the memory, the bridge apparatus causes the first master apparatus and the second master apparatus to communicate via a first slave circuit, a second slave circuit in which an address corresponding to the first address is set, and the bus, based on the addresses of the memories.