Systems and methods for a content addressable cache that is optimized for SSD use are disclosed. In some embodiments, the cache utilizes an identifier array where identification information is stored for each entry in the cache. However, the size of the bit field used for the identification information is not sufficient to uniquely identify the data stored at the associated entry in the cache. A smaller bit field increases the likelihood of a “false positive”, where the identification information indicates a cache hit when the actual data does not match the digest. A larger bit field decreases the probability of a “false positive”, at the expense of increased metadata memory space. Thus, the architecture allows for a compromise between metadata memory size and processing cycles.

A hybrid drive and associated methods increase the rate at which data are transferred to a nonvolatile storage medium in the hybrid drive. By using a large nonvolatile solid state memory device as cache memory for a magnetic disk drive, a very large number of write commands can be cached and subsequently reordered and executed in an efficient manner. In addition, strategic selection and reordering of only a portion of the write commands stored in the nonvolatile solid state memory device increases efficiency of the reordering process.

In accordance with one implementation, a method for mitigating cache transfer time entails reading data into memory from at least two consecutive elliptical data tracks in a main store region of data storage and writing the data read from the at least two consecutive elliptical data tracks to a spiral data track within a cache storage region.

An emulation mitigation module is configured to mitigate emulation of legacy write requests on advanced disk devices using cached data stored in a cache memory of a storage system. A legacy write request may comprise write data blocks formatted in a legacy sector size while an advanced disk device may be formatted in an advanced sector size. The emulation mitigation module may execute a first method for modifying write requests using cached data, a second method for enforcing a minimum requested data size sent to the advanced disk device, and/or a third method for conditionally retrieving data from the advanced disk device and storing to cache. In some embodiments, the second and/or third method may be used with the first method to increase the effectiveness of the first method. The emulation mitigation module may improve performance and/or data integrity for of processing legacy write requests.

A method for writing data objects, the method may include accumulating, in a first memory module, multiple new data entities in one or more dirty pages of a data layer; wherein each new data entity and a corresponding older data entity are associated with a same application object; wherein the accumulating comprises storing each new data entity in a page that differs from a page that stores the corresponding older data entity; calculating multiple new sets of descriptors by generating to each new data entity, a new set of descriptors; wherein each set of descriptors comprises descriptors that belong to multiple descriptors layers; wherein the multiple descriptors layers and the data layer belong to an hierarchical data structure; accumulating the multiple new sets of descriptors in one or more dirty pages of one or more descriptors layers; wherein each corresponding older data entity is associated with a corresponding set of descriptors; wherein the accumulating comprises storing each new set of descriptor in a page that differs from a page that stores a corresponding set of descriptors; and writing the multiple new data entities and the multiple new sets of descriptors to a second memory module.

A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory comprising a plurality of NVM lines. For each unconditional change of flow instruction, the method comprises establishing a NVM line address of the NVM line containing said unconditional change of flow instruction; establishing a destination address associated with the unconditional change of flow instruction; determining whether the destination address is in an address range corresponding to a NVM-pre-fetch starting from said NVM line address; establishing a pre-fetch flag indicating whether the destination address is in the address range corresponding to a NVM-pre-fetch starting from said NVM line address; and recording the pre-fetch flag in a pre-fetch control information record.

A memory page management method is provided. The method includes receiving a state-change notification corresponding to a state-change page, and grouping the state-change page from a list to which the state-change page belongs into a keep list or an adaptive LRU list of an adaptive adjusting list according to the state-change notification; receiving an access command from a CPU to perform an access operation to target page data corresponding to a target page; determining that a cache hit state is a hit state or a miss state according to a target NVM page address corresponding to the target page, and grouping the target page into the adaptive LRU list according to the cache hit state; and searching the adaptive page list according to the target NVM page address to obtain a target DRAM page address to complete the access command corresponding to the target page data.

The present disclosure includes apparatuses and methods related to a memory system including a filter. An example apparatus can include a filter to store a number flags, wherein each of the number of flags corresponds to a cache entry and each of the number of flags identifies a portion of the memory device where data of a corresponding cache entry is stored in the memory device.

A cache space management method and apparatus are disclosed. In the method, first, a hit rate of the read cache of the storage system is obtained; and then, a size of the read cache and a size of the metadata cache are adjusted based on the hit rate of the read cache. In the foregoing technical solution, the size of the read cache and the size of the metadata cache are dynamically adjusted by using the hit rate of the read cache as a decision factor. For example, when the hit rate of the read cache is relatively high, the size of the read cache may be increased.

A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.