A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

A data processing system includes support for sub-page granular memory tags. The data processing system comprises at least one core, a memory controller responsive to the core, random access memory (RAM) responsive to the memory controller, and a memory protection module in the memory controller. The memory protection module enables the memory controller to use a memory tag value supplied as part of a memory address to protect data stored at a location that is based on a location value supplied as another part of the memory address. The data processing system also comprises an operating system (OS) which, when executed in the data processing system, manages swapping a page of data out of the RAM to non-volatile storage (NVS) by using a memory tag map (MTM) to apply memory tags to respective subpages within the page being swapped out. Other embodiments are described and claimed.

Technology for a system operable to allocate physical pages of memory is described. The system can include a memory side cache, a memory side cache monitoring unit coupled to the memory side cache, and an operating system (OS) page allocator. The OS page allocator can receive feedback from the memory side cache monitoring unit. The OS page allocator can adjust a page allocation policy that defines the physical pages allocated by the OS page allocator based on the feedback received from the memory side cache monitoring unit.

Methods and apparatus for computer systems having first and second memory tier having regions, physical memory having page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier, and virtual memory having mmaps of ones of the regions in the first memory tier and ones of the regions in the second memory tier, wherein the mmaps are associated with multiple ones of the pages caches.

An improved architectural means to address processor cache attacks based on speculative execution defines a new memory type that is both cacheable and inaccessible by speculation. Speculative execution cannot access and expose a memory location that is speculatively inaccessible. Such mechanisms can disqualify certain sensitive data from being exposed through speculative execution. Data which must be protected at a performance cost may be specifically marked. If the processor is told where secrets are stored in memory and is forbidden from speculating on those memory locations, then the processor will ensure the process trying to access those memory locations is privileged to access those locations before reading and caching them. Such countermeasure is effective against attacks that use speculative execution to leak secrets from a processor cache.

Methods and apparatus for providing region zero-fill on demand for tiered memory including a first region in a first memory tier having a page cache in physical memory, where virtual memory includes a mmap of the first region. An input can be controlled between zeroes and the first region to the page cache.

Disclosed are a method and a device for increasing the performance of processes through cache splitting in a computing device using a plurality of cores. According to the present invention, a cache splitting method for performing a cache splitting in a computing device comprises the steps of: identifying, among a plurality of processes being executed, a process generating a cache flooding; and controlling the process generating the cache flooding such that the process uses a cache of a limited size.

A memory system implements a plurality of virtual address modification policies and optionally a plurality of cache eviction policies. Virtual addresses are optionally, selectively, and/or conditionally modified by the memory system in accordance with a plurality of virtual address modification policies. The virtual address modification policies include no modification, modification according to two-dimensional Morton ordering, and modification according to three-dimensional Morton ordering. For example, in response to a reference to a particular virtual address, the particular virtual address is modified according to two-dimensional Morton ordering so that at least two elements in a same column and distinct respective rows of a two-dimensional data structure are loaded into a same cache line and/or are referenced via a same page table entry.

A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.