Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

The present disclosure relates to a communication method by I2C bus between a emitting device and a receiving device, in which: a rising edge of a clock signal of the I2C bus, directly following a start condition of an I2C communication, is recorded; and when an interruption is generated within the receiving device, the receiving device verifies whether the rising edge was recorded.

A low voltage drive circuit includes a transmit digital to analog circuit that converts transmit digital data into analog outbound data by: generating a DC component; generating a first oscillation at a first frequency; generating a second oscillation at the first frequency; and outputting the first oscillation or the second oscillation on a bit-by-bit basis in accordance with the transmit digital data to produce an oscillating component, wherein the DC component is combined with the oscillating component to produce the analog outbound data, and wherein the oscillating component and the DC component are combined to produce the analog outbound data. A drive sense circuit drives an analog transmit signal onto a bus, wherein the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at the first frequency and wherein analog inbound data is represented within an analog receive signal as variances in loading of the bus at a second frequency.

A system and method for logging state data from a power system control device on a computer system is disclosed. The computer system includes a power system supplying power to the computer system. The power system has a power-up sequence having a plurality of stages. The power system control device is coupled to the power system. The power system control device includes a finite state machine circuit having states corresponding to the stages of the power-up sequence. The control device also has a write controller, a storage buffer, and a communication interface. The write controller writes the state of the finite state machine circuit in the storage buffer. An external controller is coupled to the communication interface and is operable to read the stored state data.

A system component having a configurable communication behavior. The system component includes at least one interface for a data bus for the communication with at least one further system component. A defined communications protocol for the transmitting and receiving of data and bus commands is used on the data bus. The communications protocol provides that the at least one further system component queries the communication behavior of the system component via the data bus to adapt its own communication behavior to that of the system component. The system component includes a register for configuration data that define the communication behavior of the system component on the data bus, the register being connected to the data bus so that the configuration data stored in the register are available on the data bus. The function scope of the system component allows for different communication behaviors.

A device includes an interface configured to connect to a communication link. A controller of the device is configured to generate a redundancy code using first data and second data, and to transmit the redundancy code together with the first data to the interface.

Apparatuses for controlling data transaction between master and slave devices are described. A master port connected to a master device can include a voltage regulator, a bridging circuit connected to a network element, and a redriver circuit. In response to a data transaction corresponding to a first type of data transaction, the master port can activate the voltage regulator and deactivate the redriver circuit to support a first operation mode causing the master device to perform the data transaction with a slave device via the network element. In response to the data transaction corresponding to a second type of data transaction, the master port can deactivate the voltage regulator and activate the redriver circuit to support a second operation mode causing the master port to disconnect from a slave port connected to the slave device and the data transaction is fulfilled by a circuit connected to the slave device.

A communication device includes an interface connector for connecting to a computing circuit to receive a media data and an external power supply, a transmission circuit, wherein the circuit transmits the media data to a network, a battery power supply, a controller circuit powered by the battery power supply, a sensor, communicatively coupled to the controller circuit, for detecting a movement of the communication device, a switch circuit for switchably connecting the battery power supply to the transmission circuit responsive to a first switch control signal, and a test circuit, communicatively coupled to the controller circuit, for generating the first switch control signal based on an external power control signal indicating whether the interface connector is connected to the computing circuit and a motion detection signal indicating whether the sensor detects the movement of the communication device.

In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. An I3C master receives a max read length and a max write length from an I3C slave. Then, when transmitting/receiving data to/from the I3C slave, the I3C master controls transmission/reception of the data so that the data to be transferred in one data transfer has a data length equal to or shorter than the max read length and the max write length, and transmits transfer length information indicating the data length of the data to be transferred, prior to data transfer of the data. The present technology is applicable to a bus IF, for example.