A storage system includes a NAND storage media and a nonvolatile storage media as a write buffer for the NAND storage media. The write buffer is partitioned, where the partitions are to buffer write data based on a classification of a received write request. Write requests are placed in the write buffer partition with other write requests of the same classification. The partitions have a size at least equal to the size of an erase unit of the NAND storage media. The write buffer flushes a partition once it has an amount of write data equal to the size of the erase unit.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Optimizing transaction traffic on a System on a Chip (SoC) by using procedures such as expanding transactions and consolidating responses at nodes of an interconnect fabric for broadcasts, multi-casts, any-casts, source based routing type transactions, intra-streaming two or more transactions over a stream defined by a paired virtual channel-transaction class, trunking physical resources sharing common logical identifier, and using hashing to select among multiple physical resources sharing a common logical identifier.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

The technology disclosed relates to interconnect-based resource allocation for reconfigurable processors. In particular, the technology disclosed relates to a runtime logic that is configured to receive target interconnect bandwidth and target interconnect latency, and rated interconnect bandwidth and rated interconnect latency. The runtime logic is further configured to respond by allocating, to configuration files defining an application graph, processing elements in a plurality of processing elements, and interconnects between the processing elements, and executing the configuration files using the allocated processing elements and the allocated interconnects.

A system is described that has a node and runtime logic. The node has a plurality of processing elements operatively coupled by interconnects. The runtime logic is configured to receive target interconnect bandwidth, target interconnect latency, rated interconnect bandwidth and rated interconnect latency. The runtime logic responds by allocating to configuration files defined by the application graph: (1) processing elements in the plurality of processing elements, and (2) interconnects between the processing elements. The runtime logic further responds by executing the configuration files using the allocated processing elements and the allocated interconnects.

Bandwidth on a front-end port of a storage system may be managed. A plurality of logical storage units may be divided into a plurality of priority groups according to a predefined priority. For a first priority group of the plurality of priority groups having a highest priority, a first forecasted average amount of bandwidth of the first port to be consumed by the logical storage units of the first priority group during a first temporal interval may be determined. Based on the first forecasted average amount, a first reserve amount of bandwidth on the first port to be reserved for use by the logical storage units of the first priority group during the first temporal interval may be determined. The first reserve amount of bandwidth on the first port for use by the logical storage units of the first priority group during the first temporal interval may be reserved.

Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.

A method of healing an image in a display system having a host device and a display control device includes generating healing updates corresponding to a region of the image and generating other display data at the host device, allocating, by the host device or the display control device, at least a portion of a resource of the display system to be used at least preferentially for at least one of encoding, decoding, transmitting and/or storing the healing updates rather than the other display data, encoding the healing updates and the other display data at the host device, transmitting the encoded healing updates and the other encoded display data from the host device to the display control device, decoding the encoded healing updates and the other encoded display data at the display control device, and healing the image using the decoded healing updates at the display control device.