An electronic device and method for communicating with an external electronic device that is connected via a connector of the electronic device are provided. The electronic device includes a connector including a first pin and a second pin, a communication interface connected with the connector, and at least one processor electrically connected with the communication interface, wherein the at least one processor may be configured to apply a first current to the first pin, determine whether liquid is introduced into the connector using the second pin, and if the liquid is introduced into the connector, apply a second current smaller than the first current to the first pin.

A hot plug method, a host controller, a host, and a PCIe bridge device. The method includes: generating, by a host controller, a first notification packet, where the first notification packet includes hot plug interruption information, and the hot plug interruption information indicates that a first PCIe device is to be hot-plugged; sending, by the host controller, the first notification packet to a host, so that the host performs, according to the first notification packet, a hot plug operation corresponding to the PCIe device; and receiving, by the host controller, a second notification packet sent by the host, and sending the second notification packet to a user equipment controller, to facilitate the user equipment controller to instruct a user to insert or remove the PCIe device, where the second notification packet is for indicating that the hot plug operation corresponding to the PCIe device is completed.

A computer system and a handling method thereof for an interrupt event are provided. The computer system includes an embedded controller, a system memory, and a processing unit. The embedded controller has an internal memory and triggers an interrupt event. The processing unit is coupled to the embedded controller and the system memory, and receives a notification of the interrupt event. In response to the interrupt event, the processing unit reads an event identifier corresponding to the interrupt event at a specific address section in the internal memory or maps the event identifier corresponding to the interrupt event at the specific address section in the internal memory of the embedded controller to the system memory. The processing unit notifies a hardware driver program corresponding to the event identifier. Accordingly, efficiency of handling the interrupt event is effectively enhanced.

Systems and methods for directly updating the virtual machine memory by interrupt handlers. An example method may comprise: receiving, by a computer system, an interrupt triggered by a physical device; receiving, by an interrupt handling routine, a data frame from the physical device; identifying a virtual machine to receive the interrupt; and responsive to determining that an active memory context on the computer system matches a memory context of the virtual machine, writing, by the interrupt handling routine, the data frame into a memory of the virtual machine.

In a system constructed by a plurality of integrated circuits, interrupt control can be performed in the case where an interrupt has occurred in an integrated circuit in which the function of a CPU is suspended. An interrupt unit of a second integrated circuit outputs an interrupt to at least one of the plurality of image processing units of the second integrated circuit, an image processing unit of the second integrated circuit, to which the interrupt is input, outputs an interrupt to a first integrated circuit, an image processing unit of the first integrated circuit, to which an interrupt from the second integrated circuit is input, outputs an interrupt to an interrupt unit of the first integrated circuit, and the interrupt unit of the first integrated circuit outputs an interrupt to an control unit of the first integrated circuit in accordance with the interrupt being input.

A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

A technique for handling interrupts in a data processing system includes receiving, at an interrupt presentation controller (IPC), an event notification message (ENM) that specifies an event target number and a number of bits to ignore. In response to a slot being available in an interrupt request queue, the IPC enqueues the ENM in the slot. In response to the ENM being dequeued from the interrupt request queue, the IPC determines a group of virtual processor threads that may be potentially interrupted based on the event target number and the number of bits to ignore specified in the ENM. The event target number identifies a specific virtual processor thread and the number of bits to ignore identifies the number of lower-order bits to ignore with respect to the specific virtual processor thread when determining a group of virtual processor threads that may be potentially interrupted.

An electronic device and method for communicating with an external electronic device that is connected via a connector of the electronic device are provided. The electronic device includes a connector including a first pin and a second pin, a communication interface connected with the connector, and at least one processor electrically connected with the communication interface, wherein the at least one processor may be configured to apply a first current to the first pin, determine whether liquid is introduced into the connector using the second pin, and if the liquid is introduced into the connector, apply a second current smaller than the first current to the first pin.