G06F2213/24

Composite ply-by-ply damage assessment using correlation factors between finite element models (FEMs) and non-destructive evaluations (NDEs)

A computer is configured to enable a rapid, consistent, ply-by-ply, quantitative analytical assessment of various Finite Element Method (FEM) material models based on metrics defined for impact damage. Additionally, the computer is configured to provide a method for determining the accuracy of such FEM material model(s) by comparing the output of those models to non-destructive evaluation (NDE) test data.

Secure environment in a non-secure microcontroller

A secure engine method includes providing an embedded microcontroller in an embedded device, the embedded microcontroller having internal memory. The method also includes providing a secure environment in the internal memory. The secure environment method recognizes a boot sequence and restricts user-level access to the secure environment by taking control over the secure environment memory. Taking such control may include disabling DMA controllers, configuring at least one memory controller for access to the secure environment, preventing the execution of instructions fetched from outside the secure environment, and only permitting execution of instructions fetched from within the secure environment. Secure engine program instructions are then executed to disable interrupts, perform at least one secure operation, and re-enable interrupts after performing the at least one secure operation. Control over the secure environment memory is released, which can include clearing memory, re-enabling DMA controllers, and restoring memory controller parameters.

VIRTUALIZATION OF INTERPROCESSOR INTERRUPTS
20220365802 · 2022-11-17 · ·

Embodiments of apparatuses, methods, and systems for virtualization of interprocessor interrupts are disclosed. In an embodiment, an apparatus includes a plurality of processor cores; an interrupt controller register; and logic to, in response to a write from a virtual machine to the interrupt controller register, record an interprocessor interrupt in a first data structure configured by a virtual machine monitor and send a notification of the interprocessor interrupt to at least one of the plurality of processor cores.

DYNAMIC MEMORY PROTECTION DEVICE SYSTEM AND METHOD
20220358062 · 2022-11-10 · ·

A microcontroller includes a memory, direct memory access (DMA) controllers and a microprocessor. The microprocessor maintains one or more memory protection (MP) configurations to control access to protected memory areas of the microcontroller. In response to a secure service call of an unsecure user-application, the microprocessor executes a state machine which disables interrupt requests, determining whether DMA controller configurations and MP configurations satisfy secure-service criteria. When the secure-service criteria are satisfied, at least one secure operation associated with the secure service call is performed, and memory areas accessed during the execution of the at least one secure operation are cleaned. The interrupt requests are re-enabled and a response to the secure service call is generated.

Electronic device, interrupt configuration control method, and storage medium

An electronic device includes a peripheral device, a processor, an interrupt controller configured to manage interrupts generated by the peripheral device and the processor on the basis of a register, and a virtualizer, wherein the virtualizer may be configured to virtualize a portion of the processor and a portion of the at least one peripheral device to generate a first partition, generate first interrupt information corresponding to an interrupt usable in the first partition, generate first processor information corresponding to a portion of the processor usable in the first partition, check whether a configuration of the register is related to at least one of the first interrupt information and the first processor information when the register is configured by the first partition, and allow the configuration of the register when the configuration of the register is related to the at least one information.

Photodynamic energy electronic label, working method thereof, managing method and managing apparatus thereof

The present disclosure provides a photodynamic energy electronic label, a working method thereof, a managing method and a managing apparatus thereof. The photodynamic energy electronic label includes a photodynamic energy converter configured to convert light energy into electric energy, and a triggering circuit connected with the photodynamic energy converter and configured to send out a triggering signal to enable the photodynamic energy electronic label to be in a working state when an output of the photodynamic energy converter reaches a set condition.

Application processor supporting interrupt during audio playback, electronic device including the same and method of operating the same
11256638 · 2022-02-22 · ·

An application processor includes a system bus, as well as a host processor, a voice trigger system, and an audio subsystem that are electrically connected to the system bus. The voice trigger system performs a voice trigger operation and issues a trigger event based on a trigger input signal that is provided through a trigger interface. The audio subsystem processes audio streams that are replayed or recorded through an audio interface, and receives an interrupt signal through the audio interface while an audio replay operation is performed through the audio interface.

DIRECTED INTERRUPT VIRTUALIZATION WITH FALLBACK

A processor receives an interrupt signal. The interrupt signal is received with an interrupt target ID identifying a target processor for handling the interrupt signal. The processor is a target of the interrupt signal directly. A check is made as to whether the processor is the target processor identified by the interrupt target ID. The checking includes performing a comparison of the interrupt target ID with a current interrupt target ID assigned to the processor. Based on the checking being successful, the interrupt signal is accepted for handling by the processor.

INTERRUPT REQUEST SIGNAL CONVERSION SYSTEM AND METHOD, AND COMPUTING DEVICE
20220229794 · 2022-07-21 ·

An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

Dynamic assignment of interrupts based on input/output metrics

A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system. The interrupt manager uses hint data provided by the device driver to make the interrupt assignments.