The present disclosure provides a photodynamic energy electronic label, a working method thereof, a managing method and a managing apparatus thereof. The photodynamic energy electronic label includes a photodynamic energy converter configured to convert light energy into electric energy, and a triggering circuit connected with the photodynamic energy converter and configured to send out a triggering signal to enable the photodynamic energy electronic label to be in a working state when an output of the photodynamic energy converter reaches a set condition.

An interrupt request signal conversion system includes an interrupt request signal converter configured to generate one or more converted interrupt request signals based on one or more signals received from one or more peripheral devices, and a signal output terminal configured to send the one or more converted interrupt request signals to an interface module of a processor during operation. Each of the one or more converted interrupt request signals includes a plurality of interrupt identification bits each used to identify, based on a first level and a second level different from the first level, whether a signal received from a corresponding one of the one or more peripheral devices within a predetermined time range includes a peripheral interrupt request signal.

An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

Example computer-implemented methods, media, and systems for processing input/output (I/O) commands using block size aware polling are disclosed. One example method includes creating multiple polling queues and multiple interrupt queues in a transport drivers layer of a storage stack. A first I/O command is received from a core layer of the storage stack and by the transport drivers layer. A ratio of a total number of multiple small block size commands in the transport drivers layer to a total number of multiple outstanding I/O commands in the transport drivers layer is determined to be larger than a predetermined first threshold. In response to determining that the ratio is larger than the predetermined first threshold, the polling mode is applied to the first I/O command through the submission of the first I/O command to a first polling queue in the multiple polling queues.

An interrupt signal is provided to a guest operating system executed using one or more processors of a plurality of processors. One of the processors receives from a bus attachment device an interrupt signal issued by a bus connected module. A logical processor ID resulting from a translation of an interrupt target ID provided with the interrupt signal is used to address the receiving processor directly. The receiving processor checks whether interrupt target ID identifies the receiving processor as a target processor of the interrupt signal. If the receiving processor is not the target processor, the interrupt signal is forwarded for handling by the guest operating system using broadcasting.

An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

An electronic device includes a peripheral device, a processor, an interrupt controller configured to manage interrupts generated by the peripheral device and the processor on the basis of a register, and a virtualizer, wherein the virtualizer may be configured to virtualize a portion of the processor and a portion of the at least one peripheral device to generate a first partition, generate first interrupt information corresponding to an interrupt usable in the first partition, generate first processor information corresponding to a portion of the processor usable in the first partition, check whether a configuration of the register is related to at least one of the first interrupt information and the first processor information when the register is configured by the first partition, and allow the configuration of the register when the configuration of the register is related to the at least one information.

An I/O controller includes a port to couple to a network, a buffer to buffer network data, and an interface to support a link to couple the I/O controller to another device. The I/O controller monitors a buffer to determine an amount of traffic on the port, initiates, at the interface, a power management transition on the link based on the amount of traffic, and mitigate latency associated with the power management transition at the port.

A system and method dynamically assign interrupts to a virtual machine from an input/output (I/O) adapter based on I/O metrics of the I/O adapter. An interrupt manager monitors I/O adapter traffic flow metrics such as latency of data transfers, usage levels, and transfers per unit of time. The interrupt manager determines when a traffic flow metric for a virtual machine meets a predetermined performance threshold and updates virtual interrupt assignments in a logical interrupt table to improve performance of the system. The interrupt manager uses hint data provided by the device driver to make the interrupt assignments.

A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.