A system includes an application processor configured to generate a read request and including a data memory; a host processor configured to generate a read command corresponding to the read request; and a data storage device including a data storage memory, wherein the data storage device transmits read data output from the data storage device according to the read command to the data memory of the application processor without passing the host processor.

System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.

A system includes an application processor configured to generate a read request and including a data memory; a host processor configured to generate a read command corresponding to the read request; and a data storage device including a data storage memory, wherein the data storage device transmits read data output from the data storage device according to the read command to the data memory of the application processor without passing the host processor.

A system includes a direct memory access controller and a memory coupled to the direct memory access controller. The memory stores a linked list of records. Each record contains a first field determining the number of fields of a next record. For example, each record can be representative of parameters of execution of a data transfer by the direct memory access controller.

System and techniques for enhanced electronic navigation maps for a vehicle are described herein. A descriptor set-up message may be received at a network controller interface (NIC). Here, the descriptor set-up message includes an ethernet frame descriptor. The NIC may then use the ethernet frame descriptor to transmit, across a physical interface of the NIC, multiple ethernet frames, each of which use the same ethernet frame descriptor from the set-up message.

A data processing pipeline controller receives a request, from a data iterator associated with a machine learning model, for a data output of a module in the data processing pipeline, wherein each module in the data processing pipeline has an associated cache. The controller determines whether a data output of the module is stored in the associated cache and responsive to the data output being stored in the associated cache, provides the data output from the associated cache to the data iterator without processing data through the module.

Disclosed herein are techniques associated with a Direct Memory Access (DMA) engine that can include a data generation module. The DMA engine can receive, from a processing entity, a particular type of write command with an indicator to write a data pattern to an address. Upon receipt of the particular type of write command, the DMA engine can generate, using a data generation module of the DMA engine, the data pattern to be written to the address. The processing entity can be Central Processing Unit (CPU) including a core configured to process serial commands. The DMA engine can be disposed on a same die as a processing entity or a network interface port.

A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.

In one example, an apparatus comprises: a direct memory access (DMA) descriptor queue that stores DMA descriptors, each DMA descriptor including an indirect address; an address translation table that stores an address mapping between indirect addresses and physical addresses; and a DMA engine configured to: fetch a DMA descriptor from the DMA descriptor queue to the address translation table to translate a first indirect address of the DMA descriptor to a first physical address based on the address mapping, and perform a DMA operation based on executing the DMA descriptor to transfer data to or from the first physical address.