G06F2213/3602

Method and apparatus to enable multiple masters to operate in a single master bus architecture

To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to assert an in-band IRQ. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.

CHIP SELECT TRANSMITTERS FOR MULTIPLE SIGNAL LEVELS
20240347099 · 2024-10-17 ·

A signal driving circuit includes a first transmitting circuit having an input coupled to a source of a chip select signal and an output that is configured to switch within a first voltage range having a first amplitude, a second transmitting circuit having an input coupled to the source of the chip select signal and an output that is configured to switch within a second voltage range having a second amplitude, and an output node coupled to the output of the first transmitting circuit and the output of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

RADIO FREQUENCY INTERFERENCE COMMON MODE INJECTION IN A C-PHY RECEIVER

An input buffer includes a pair of input transistors and associated injection circuits. A first input transistor has a source coupled to a first voltage rail through a first current source and a gate coupled to a first wire of a multi-wire serial bus. Three or more resistors in a first injection circuit couple the wires of the serial bus to a first common node, which is coupled to the source of the first input transistor by a first capacitor. A second input transistor has a source coupled to the first voltage rail through a second current source and a gate coupled to a second wire of the serial bus. Three or more resistors in a second injection circuit couple the wires of the multi-wire serial bus to a second common node, which is coupled to the source of the second input transistor by a second capacitor.

BI-DIRECTIONAL COMMUNICATION BASED CONTROL APPARATUS AND SYSTEM, AND BI-DIRECTIONAL COMMUNICATION INTERFACE
20250272259 · 2025-08-28 · ·

The present disclosure relates to a bi-directional communication-based control apparatus and system, and a bi-directional communication interface. The technical problem to be solved provides topology capable of implementing hardwired contactor control using a single port of a micro controller unit (MCU) without being constrained by restrictions on the number of ports of the MCU which may be required depending on design specifications of an electronic control unit (ECU) and a battery management system (BMS). To this end, the present disclosure provides a processor that controls a target element according to a control signal applied to a communication bus and causes state information of the target element according to a result of the control to be formed on a communication bus, the control signal being input and a state signal for forming the state information being output through a single bi-directional port provided in the processor; and an arbitrator that arbitrates first direction transmission of the control signal from the communication bus to the bi-directional port and second direction transmission of the state signal from the bi-directional port to the communication bus.

Chip select transmitters for multiple signal levels
12424265 · 2025-09-23 · ·

A signal driving circuit includes a first transmitting circuit having an input coupled to a source of a chip select signal and an output that is configured to switch within a first voltage range having a first amplitude, a second transmitting circuit having an input coupled to the source of the chip select signal and an output that is configured to switch within a second voltage range having a second amplitude, and an output node coupled to the output of the first transmitting circuit and the output of the second transmitting circuit. The first amplitude may be lower than the second amplitude.

INFORMATION TRANSCEIVING METHOD AND INFORMATION TRANSCEIVING SYSTEM
20260058729 · 2026-02-26 · ·

An information transceiving method, applied to an information transceiving system comprising a transmission device and a reception device. The transmission device comprises a first TX input interface following a first transceiving specification and a second TX input interface following a second transceiving specification. The reception device comprises a first RX output interface following a third transceiving specification. The information transceiving method comprises: (a) respectively receiving first, second information by the first, second TX input interface; (b) classifying according to information characteristics of the first, second information by the transmission device, to acquire first, second classifying results of the first, second information; and (c) transmitting the first information or the second information to the first RX output surface via a physical transmission line, corresponding to the first, second classifying results by the transmission device.

Information feedback method and serial communication system

An information feedback method can include: transmitting, by a master device, an instruction to acquire specific information, where each of a plurality of slave devices when receiving the instruction serves as the current slave device; configuring the current slave device in the communication link in the first mode to receive the instruction from the master device or a previous slave device, and forwarding the instruction to a next slave device; connecting input port SDI and output port SDO of the current slave device by controlling the current slave device in the second mode to form a first pathway; determining, by the current slave device, whether the specific information is present in the current slave device to obtain a corresponding determination result; and then selectively configuring, by the current slave device, a potential of the first pathway of the current slave device to be at a first level.