A modular system is described which can provide high frequency monitoring of power use and responsive control as well as enabling network connectivity for centralised monitoring and operation. One modular system consists of a communications bus, end caps, and a combination of the modules providing communications, power metering, relay control and battery backup. Each modular system can be configured with a combination of modular units as needed for the application. A combination of bus communication monitoring and tilt detection provides security against external tampering after installation.

A vehicle information service implemented on one or more computers of a service provider network implements a first application programmatic interface (API) that allows a client to define inclusion parameters and a sample size for a fleet of vehicles from which vehicle data is to be collected. The vehicle information service also implements a second API that notifies the client when the requested vehicle data has been collected from the vehicle fleet. Additionally, the vehicle information service provides the client access to the collected vehicle data. The vehicle information service manages the collection of the vehicle data from the client defined vehicle fleet without requiring further client involvement and notifies the client when the collection of the vehicle data is complete.

A chip-to-chip interface of a multi-chip module (MCM), including: bidirectional data links for transmitting data signals and a direction indicator bit, wherein the direction indicator bit switches a direction of the bidirectional data links in real-time; a clock link for transmitting a clock signal common to the bidirectional data links, wherein the data and clock links are comprised of conductive traces between the chips and laid out to be of substantially equal length; and a clock driver means having a digitally programmable clock signal delay.

An electronic component (10) is formed by a semiconductor component or a semiconductor-like structure having gate electrode assemblies (16, 18), for initializing the quantum mechanical state of a qubit.

The present invention provides a frequency-halving latch circuit for deterministic field bus network data forwarding and application thereof. The frequency-halving latch circuit includes a data buffer equipped with two buffer units; a frequency-halving enable latch signal generation module for generating a first frequency-halving latch signal and a second frequency-halving latch signal with opposite levels, and selecting data buffer units of the data buffer based on the first frequency-halving latch signal, the second frequency-halving latch signal and a receiving enable signal; and a shift register including a first trigger and a second trigger which are initialized to opposite output states, the first trigger and the second trigger is connected to realize a shift operation, and data stored in the data buffer units is finally selected and read based on a low order in the shift register composed of the two triggers and a read enable signal. The frequency-halving latch circuit can be applied to a scenario of deterministic field bus network data forwarding as a same-frequency out-of-phase data cross-clock domain circuit, with high resource utilization rate and stability.

The invention relates to a method for communicating data between communication equipments, where the first communication equipment (EqptN) is put into the emission mode (Xmit) for the frame (TrN) containing its identification (D_PID), while each second communication equipment (Eqpt1, EqptN+1, EqptN+x) is put into the receiving mode (Rcv), then the equipment (EqptN) is put into the receiving mode (Rcv), each equipment (Eqpt1, EqptN+1, EqptN+x) prescribes its local emission window (Ftle1, FtleN+1, FtleN+x), which is associated with its identification, during which it is put into the emission mode (Xmit) for its frame, a time of beginning (IDF1, IDFN+1, IDFN+X) of the window being a determined function, increasing with respect to a difference equal to its identification from which the identification (D_PID) is subtracted, each equipment is put into the emission mode, during which it emits its frame containing its identification during its window starting at the beginning time.

In a stacked integrated circuit device, there are two components, one in a first of the die and another in a second of the die. Each of the components is provided with two output connections, one leading above and one leading below the die, and two input connections, one leading above and one leading below the die, either of the two die. As a result of the redundancy, both die may be used in either position in the stacked structure. If either of the die is used as the top die, it sends data on its second output path and receives data on its second input path. On the other hand, when one of the die is used as the bottom die, it sends data on its first output path and receives data on its first input path. In this way, the same design may be used for the connections between each of the die.

A supervisory unit configured to supervise interconnect messages passing to or from an interconnect is provided. The supervisory unit is configured to, on receiving an interconnect message: store the interconnect message in a data store; compare the interconnect message to predetermined filter criteria; and select, in dependence on that comparison, one or more actions to be taken with respect to the interconnect message. The one or more actions are selected from the group including: permitting the interconnect message to pass unaltered; blocking the interconnect message from passing and permitting the interconnect message to pass in an altered state; and performing the one or more selected actions with respect to the interconnect message.

An input switching circuit dynamically connects, based on an input mapping table, input streams to inputs of a wavefront pre-transform circuit. An output switching circuit dynamically connects, based on an output mapping table, output data at outputs of the wavefront pre-transform circuit to transport streams. A controller controls, based on a wiping command, at least one of the input and output switching circuits to alter at least one of the input and output mapping tables such that the at least one of the input and output switching circuits is disabled for connection. A first subset of the transport streams operates in a foreground mode available to a user and is transported for storage in remote storage sites at a network and a second subset of the transport streams operates in a background mode available to an administrator and is not transported for storage in the remote storage sites.

A reconfigurable hardware platform uses, in place of a portion of software, a chain of reconfigurable hardware Operator Blocks to manipulate data as the data moves down the chain. This conveyor belt architecture, or chain of Operator Blocks, moves data from Operator Block to Operator Block. This conveyor belt architecture processor may be combined with a conventional front-end processor to process complex information or critical loops in hardware while processing a rest of a program as software.