Implementations disclosed describe methods and systems to perform the methods of optimizing a size of memory used for accumulation of neural node outputs and for supporting multiple computational paths in neural networks. In one example, a size of memory used to perform neural layer computations is reduced by performing nodal computations in multiple batches, followed by rescaling and accumulation of nodal outputs. In another example, execution of parallel branches of neural node computations include evaluating, prior to the actual execution, the amount of memory resources needed to execute a particular order of branches sequentially and select the order that minimizes this amount or keeps this amount below a target threshold.

A computer-implemented method, according to one embodiment, includes: storing records in an input data buffer, where each of the records include a key which is appended to payload data in the respective record. Moreover, for each of the records: shearing the key associated with the record from the payload data, normalizing the sheared key, and storing the normalized sheared key in a first target area of memory. A determination is made as to whether a size of the payload data in the record is outside a predetermine range, and in response to determining that the size of the payload data in the record is outside the predetermine range, the payload data is stored in a second target area of memory. A data locator is also appended to the normalized sheared key in the first target area of memory to form a sheared record.

One embodiment includes data communication apparatus including a storage sub-system to be connected to storage devices, and processing circuitry to manage transfer of content with the storage devices over the storage sub-system responsively to content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to availability of spare data capacity of the storage sub-system, find a malfunctioning storage device currently assigned a given data capacity of the storage sub-system and currently assigned to serve at least one content transfer request, and reallocate the given data capacity of the storage sub-system currently assigned to the malfunctioning storage device for use by at least another one of the storage devices while the at least one content transfer request assigned to be served by the malfunctioning storage device is still awaiting completion by the malfunctioning storage device.

There is provided a method for managing a solid state storage system with hybrid storage technologies. The method includes monitoring one or more storage request streams to identify operating mode characteristics therein from among a set of possible operating mode characteristics. The set of possible operating mode characteristics correspond to a set of available operating modes of the hybrid storage technologies. The method further includes identifying a current operating mode from among the set of available operating modes responsive to the identified operating mode characteristics. The method also includes predicting a likely future operating mode responsive to variations in workload requirements to generate at least one future operating mode prediction. The method additionally includes controlling at least one of data placement, wear leveling, and garbage collection, responsive to the at least one future operating mode prediction.

A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

A memory module is provided. The memory module includes: a control chip, at least one data flash memory chip, at least two memory cells, and at least one non-volatile memory, each of the at least one data flash memory chip is connected to at least one of the at least two memory cells and at least one of the at least one non-volatile memory, the control chip is connected to the at least one data flash memory chip and the at least two memory cells, and the memory is further connected to at least one capacitor; the control chip is configured to send a control command; and each of the at least one data flash memory chip is configured to perform, based on the control command from the control chip, data processing between the memory cell connected thereto and the non-volatile memory connected thereto.

Aspects of the disclosure are directed to hardware interconnects and corresponding devices and systems for non-coherently accessing data in shared memory devices. Data produced and consumed by devices implementing the hardware interconnect can read and write directly to a memory device shared by multiple devices, and limit coherent memory transactions to relatively smaller flags and descriptors used to facilitate data transmission as described herein. Devices can communicate less data on input/output channels, and more data on memory and cache channels that are more efficient for data transmission. Aspects of the disclosure are directed to devices configured to process data that is read from the shared memory device. Devices, such as hardware accelerators, can receive data indicating addresses for different data buffers with data for processing, and non-coherently read or write the contents of the data buffers on a memory device shared between the accelerators and a host device.

An information processing apparatus performs first migration processing of migrating data from a relatively-old-generation magnetic tape included in one storage pool of a plurality of storage pools to relatively-new-generation magnetic tapes included in each of the plurality of storage pools in a case where a total value of free capacities of the relatively-new-generation magnetic tapes in each of the plurality of storage pools is equal to or larger than a threshold value, and performs second migration processing of migrating data from a plurality of migration-source magnetic tapes included in the storage pool to migration-destination magnetic tapes of which the number is smaller than the number of the migration-source magnetic tapes in a case where the total value is smaller than the threshold value.

An illustrative method includes receiving a write request to write payload data to a virtual storage volume; transmitting the write request to a plurality of storage nodes each storing a replica of the virtual storage volume; acknowledging the write request only after a quorum of the storage nodes has stored the payload in their respective kernel memory; and flushing the payloads stored in each kernel memory to persistent storage only after a threshold number of outstanding write requests that have been acknowledged, but not yet flushed, has been reached, the flushing configured to optimize performance for synchronous workloads.

A memory controller, a memory system and a method of operating a memory controller controlling a memory device are described. The memory controller may include a workload manager in communication with the memory device in which data is written and is read, the workload manager configured to acquire an amount of write data written to the memory device during a preset reference time, calculate a workload parameter indicating a ratio of the amount of write data to a reference write amount, and store the workload parameter for the preset reference time, and a performance manager configured to control, based on the workload parameter, a certain background operation performed by the memory device during a period corresponding to the workload parameter.