A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.

The present application relates to a semiconductor memory training method and related devices, belonging to the technical field of semiconductors. The method comprises: obtaining a stored historical training result of a semiconductor memory, the historical training result comprising a historical expected delay value and a historical expected voltage; setting a delay threshold and a current training voltage range, the delay threshold being less than or equal to the historical expected delay value, the current training voltage range comprising the historical expected voltage; obtaining a current minimum delay value for the semiconductor memory under the historical expected voltage; and using the stored historical training result as a current training result of the semiconductor memory, if the current minimum delay value for the semiconductor memory under the historical expected voltage is no less than the delay threshold.

An apparatus which includes a first solid state drive (SSD) located on an SSD card having a fixed capacity and a first form factor. The apparatus can further include an adapter located on the SSD card to accommodate a second SSD. The second SSD has a second form factor that is different than the first form factor and is removeable from the SSD card. The apparatus can further include a controller located on the SSD card and configured to access the first SSD and the second SSD.

Provided is a three-dimensional storage device using wafer-to-wafer bonding. A storage device includes a first chip including a first substrate and a peripheral circuit region including a first control logic circuit configured to control operation modes of the non-volatile memory device and a second chip including a second substrate and three-dimensional arrays of non-volatile memory cells. The second chip may be vertically stacked on the first chip so that a first surface of the first substrate faces a first surface of the second substrate, and a second control logic circuit is configured to control operation conditions of the non-volatile memory device and is arranged on a second surface of the second substrate, the second surface of the second substrate being opposite to the first surface of the second substrate of the second chip.

Multiple data paths may be available to a data management system for transferring data between a primary storage device and a secondary storage device. The data management system may be able to gain operational advantages by performing load balancing across the multiple data paths. The system may use application layer characteristics of the data for transferring from a primary storage to a backup storage during data backup operation, and correspondingly from a secondary or backup storage system to a primary storage system during restoration.

Multiple data paths may be available to a data management system for transferring data between a primary storage device and a secondary storage device. The data management system may be able to gain operational advantages by performing load balancing across the multiple data paths. The system may use application layer characteristics of the data for transferring from a primary storage to a backup storage during data backup operation, and correspondingly from a secondary or backup storage system to a primary storage system during restoration.

A semiconductor memory device according to the present disclosure includes: a memory cell array including a plurality of planes; a command processing unit configured to generate an internal command to be executed by at feast one plane among the plurality of planes on the basis of external commands received from an external controller; a status register configured to store status information of the external commands by a tag included in the external command according to results of performing the internal command.

According to an embodiment, an electronic device includes: at least one processor and a memory configured to store instructions that can be executed by the processor, wherein the processor may be configured to: monitor information about the storage space of the memory and usage histories of a plurality of objects executed by the processor, determine a target object, of which the compile scheme is to be changed, among the plurality of objects based on at least one of the information and the usage histories; and increase the free storage space of the memory by changing the compile scheme of the target object.

Provided are a cluster arbitration method and system based on heterogeneous storage, and a device and a storage medium. The method comprises: configuring heartbeat between every two adjacent nodes in a cluster (S1); in response to the occurrence of disconnection of the heartbeat between nodes, dividing the nodes in the cluster into a plurality of sub-clusters on the basis of the disconnected heartbeat, and determining whether a sub-cluster with the largest number of nodes is unique (S2); in response to the sub-cluster with the largest number of nodes not being unique, selecting a node from each sub-cluster with the largest number of nodes and also sending a reservation request to a third-party storage logical volume (S3); in response to there being a successfully reserved node, determining whether arbitration data in the third-party storage logical volume is valid (S4); and in response to the arbitration data in the third-party storage logical volume being invalid, writing arbitration information of the successfully reserved node into the third-party storage logical volume, such that the sub-cluster, where the node is located, obtains a control right of the cluster (S5). By means of an existing configuration, storage cluster arbitration is realized without occupying additional network bandwidths.

A semiconductor memory and a method for density configuration of a bank of the semiconductor memory are provided. The method includes: determining a target bank to be configured of the semiconductor memory; determining a density configuration parameter of the target bank, the density configuration parameter being configured to represent a density to be configured for the target bank; determining a target code from a set of codes of the target bank based on the density configuration parameter of the target bank, the target code corresponding to a storage region to be trimmed in the target bank; generating, based on the target code, a region selection signal configured to select the storage region to be trimmed in the target bank; and trimming the storage region to be trimmed based on the region selection signal to configure the density of the target bank.